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1. 发明专利

JPH06311178A POLICING CIRCUIT 失效
公开(公告)号：JPH06311178A
公开(公告)日：1994-11-04
申请号：JP9606493
申请日：1993-04-22
申请人： HITACHI LTD , NIPPON TELEGRAPH & TELEPHONE , FUJITSU LTD
发明人： SHINADA SHIGEO , TAKANO MITSUHIRO , TAKASE MASAHIKO , YAMANAKA NAOAKI , SATO YOICHI , TAKEO HIROSHI , KUSAYANAGI MICHIO , IGUCHI KAZUO , TANAKA ATSUSHI
IPC分类号： G06F19/00 , H04L12/28 , H04L12/813 , H04L12/911 , H04L12/48 , G06F15/48
摘要： PURPOSE:To reduce the capacity of hardware in a policing circuit in an ATM network by block-dividing a stamp memory part by each user based on the number of allowable arriving cells and cyclicly using it within block division. CONSTITUTION:A cell detector 1 receives an input cell and detects added cell kind information. In the case of a user cell, the detector 1 detects a user identification number and outputs it and when an identification number is shown as virtual line identification data, the detector 1 detects the identification number and outputs it. A judging and comparing part 2 outputs the judging result of whether an arriving cell is normal or violating and at the time of judging it to be normal, the number of the memories of a counter memory 4 is incremented by one and a time-stamp memory part 5 time-stamps. The memory part 5 is block-divided to the number A of users and its memory area is block-divided by each user to store the output value of mobile counter in a next address shown by a pointer as an arriving time when the cell arrives. The number of the blocks is the number of the allowable cells of each user. Thereby, a memory capacity can be reduced.

2. 发明专利

JPH05252192A 失效
公开(公告)号：JPH05252192A
公开(公告)日：1993-09-28
申请号：JP5006192
申请日：1992-03-06
申请人： HITACHI LTD , NIPPON TELEGRAPH & TELEPHONE , FUJITSU LTD
发明人： TAKANO MITSUHIRO , OKABE TETSUHIRO , SHINADA SHIGEO , TAKASE MASAHIKO , YAMANAKA NAOAKI , SATO YOICHI , IGUCHI KAZUO , TAKEO HIROSHI , KUSAYANAGI MICHIO , OGURA TAKAO
IPC分类号： H04Q3/00 , G06F19/00 , H04L12/28 , H04L12/813 , H04L12/48 , G06F15/48
摘要： PURPOSE:To obtain a polishing circuit which is robust by obtaining arrival intervals by simple processing and a small hardware. CONSTITUTION:A free-running counter 2 has a predetermined maximum value set to longer than a monitor time, a time stamp generator 6 adds the monitor time to the counter value of the 7 free-running counter at the time of cell arrival to generate a process time stamp value, and a time stamp part 5 is stored with the process time value of the time stamp generator; and a resetting process part 7 subtracts the maximum value of the free-running counter 2 plus one from the process time stamp value stored in the time stamp memory part 5 and updates the process time stamp value to the subtraction result and a deciding comparator 8 calculates the arrival time between the process time stamp value generated by the time stamp generator 6 at the time of the arrival of a current arriving cell and the process time stamp value at the time of the arrival of a cell, a specific permissible number of cells before, which is stored in the time stamp memory part 5.

3. 发明专利

JPH05336147A 失效
公开(公告)号：JPH05336147A
公开(公告)日：1993-12-17
申请号：JP14453292
申请日：1992-06-04
申请人： NIPPON TELEGRAPH & TELEPHONE , FUJITSU LTD , HITACHI LTD
发明人： YAMANAKA NAOAKI , SATO YOICHI , SATO KENICHI , IGUCHI KAZUO , TAKEO HIROSHI , KUSAYANAGI MICHIO , OGURA TAKAO , TAKASE MASAHIKO , SHINADA SHIGEO , TAKANO MITSUHIRO , SAITO KIYOSHI , HOBARA KAZUHIKO , OKABE TETSUHIRO
IPC分类号： H04L12/28 , H04L12/48
摘要： PURPOSE:To obtain the high accuracy not causing a problem practically onto the management of an asynchronous communication network with small hardware configuration by executing repetitively traffic monitor for each T cell time and another T cell time whose phase is deviated by a T/2 cell time. CONSTITUTION:A counter circuit 4-1 is a circuit discriminating it that number of cells arrived within a T cell time starting from a time t0 exceeds X. A counter circuit 4-2 is a circuit discriminating it that number of cells arrived within a T cell time starting from a time [t0+T/2] exceeds X. A control circuit 2 applies a reset signal R to the counter circuits 4-1, 4-2 to reset the count for each T cell time and whose phase is deviated by a T/2 cell time alternately. When the count of the two counter circuits 4-1, 4-2 exceeds the value X, the control circuit 6 sends a discrimination output to a terminal 7.

4. 发明专利

JPH05252191A 失效
公开(公告)号：JPH05252191A
公开(公告)日：1993-09-28
申请号：JP5006092
申请日：1992-03-06
申请人： HITACHI LTD , NIPPON TELEGRAPH & TELEPHONE , FUJITSU LTD
发明人： SHINADA SHIGEO , TAKANO MITSUHIRO , YAMANAKA NAOAKI , SATO YOICHI , IGUCHI KAZUO , TAKEO HIROSHI , KUSAYANAGI MICHIO , OGURA TAKAO
IPC分类号： H04Q3/00 , G06F19/00 , H04L12/28 , H04L12/813 , H04L12/48 , G06F15/48
摘要： PURPOSE:To provide a polishing circuit with a self-operating counter which can obtain arrival intervals by a simple processing and a little increase of hardwares. CONSTITUTION:This circuit is provided with a cell detector 2 which receives a cell and detects the user identification number, a decision comparator 4 which decides illegal arrival when the arrival interval between the current arrival and arrival before the permissible number X of cells is less than a specific monitor time and normal arrival when the arrival interval is larger, the self- operating counter 5 which cyclically counts up to a specific maximum value T0, a resettable status counter 8 which counts the overflow frequency of the counter 5, and a stamp memory part 11 which is stored with the counted values of the self-operating counter 5 and status counter 8 corresponding to user identification numbers. The comparing decision unit 4 decides the arrival interval between the time of the current arriving cell and the cell which is X cells before from the respective counted values.

5. 发明专利

JPH05191433A FAULT DIAGNOSTIC SYSTEM FOR UPC CIRCUIT 失效
公开(公告)号：JPH05191433A
公开(公告)日：1993-07-30
申请号：JP302292
申请日：1992-01-10
申请人： FUJITSU LTD , NIPPON TELEGRAPH & TELEPHONE , HITACHI LTD
发明人： AMAMIYA SHIGEO , OGURA TAKAO , NAKAJO TAKAFUMI , TAKEO HIROSHI , KUSAYANAGI MICHIO , YAMANAKA NAOAKI , SATO YOICHI , TAKASE MASAHIKO , SHINADA SHIGEO , TAKANO MITSUHIRO , SAITO KIYOSHI , HOBARA KAZUHIKO , OKABE TETSUHIRO
IPC分类号： G06F11/20 , H04L12/70 , H04L12/813
摘要： PURPOSE:To provide the fault diagnostic synchronizing signal for a UPC circuit diagnosing properly a fault of the UPC circuit. CONSTITUTION:The fault diagnostic synchronizing signal for a UPC circuit controlling a cell flow based on specified information with respect to a cell traffic is provided with an active system UPC circuit W applying policing control to m-kinds of cells and a standby system UPC circuit P applying policing control to n-kinds of cells, decides policing by 2 systems or over with respect to one kind of cell or over and compares the result of decision to diagnose a fault of the UPC circuit. Furthermore, the traffic is measured by 2 systems or over with respect to one kind of cell or over and the fault of the UPC circuit is diagnosed by comparing the traffic measured values. Furthermore, q-sets of bridge memories storing prescribed information of the arrived cells in time series are provided and a fault of the bridge memory is diagnosed by comparing the content of the bridge memory by 2 systems or over.

6. 发明专利

JPH05219093A METHOD AND CIRCUIT FOR POLISHING 失效
公开(公告)号：JPH05219093A
公开(公告)日：1993-08-27
申请号：JP2097492
申请日：1992-02-06
申请人： HITACHI LTD , NIPPON TELEGRAPH & TELEPHONE
发明人： TAKASE MASAHIKO , SHINADA SHIGEO , TAKANO MITSUHIRO , OUCHI TOSHIYA , YAMANAKA NAOAKI , SATO YOICHI
IPC分类号： H04L12/813 , H04Q11/04
摘要： PURPOSE:To provide the polishing circuit for controlling the traffic which flows in violation of a report, and especially, the method for executing the detection of high accuracy by a simple constitution, in a network using an asynchronous transfer mode. CONSTITUTION:A VP/VC distributing circuit 2 distributes an ATM cell from an entry interface 1 to a traffic monitor circuit block 3 in accordance with a virtual path identifier or a virtual channel identifier. Plural counters 4-1 and 4-2 of the circuit block 3 are reset in a period T, and also, with a time shift of T/2, respectively. Comparators 5-1, 5-2 compare a counting value of each corresponding counter 4-1, 4-2 with a threshold X, and give an instruction to a rejection control circuit 9, when the counting value of either counter exceeds the value of X. Accordingly, the burst detection capacity of the polishing circuit can be doubled by a simple constitution, and the network can be utilized effectively.

7. 发明专利

JPH04186934A FAULT DECIDING SYSTEM 失效
公开(公告)号：JPH04186934A
公开(公告)日：1992-07-03
申请号：JP31405390
申请日：1990-11-21
申请人： HITACHI LTD
发明人： ITO MASAHIRO , SHINADA SHIGEO
IPC分类号： H04L29/14 , H04B17/00
摘要： PURPOSE:To execute the appropriate fault decision including a fault generated intermittently, as well by executing periodically the collection of fault information at a certain sampling timing, and executing the decision of a fault by using a certain finite pieces of sampling detection results detected before the present time point. CONSTITUTION:Fault information 1 inputted from each part in a device is subjected to ON/OFF check by a state detection holding device 2, and at the time of ON, it is held while extending over one period of a sampling timing. The result concerned is outputted as a fault information detection result 3, and inputted to an arithmetic part 4. In the arithmetic part 4, weighting is executed to the finite pieces of detection results, the sum of numerical values for which its weighting is executed is taken, and an output signal 8 is outputted. The output signal concerned is compared with a generated threshold 9 by a comparator 10, and when the signal exceeds the generated threshold, a fault generation signal 11 is obtained. Also, it is compared with a recovery threshold 12 by a comparator 13, and when it is below the recovery threshold, a fault recovery signal 14 is obtained.

8. 发明专利

JPH0322739B2 失效
公开(公告)号：JPH0322739B2
公开(公告)日：1991-03-27
申请号：JP9966581
申请日：1981-06-29
申请人： HITACHI LTD
发明人： SHINADA SHIGEO
IPC分类号： H04L7/00 , H04L7/02 , H04L7/08 , H04L27/14

9. 发明专利

JPH01164138A DIAGNOSTIC SYSTEM FOR STUFF MULTIPLEXING DEVICE 失效
公开(公告)号：JPH01164138A
公开(公告)日：1989-06-28
申请号：JP32131787
申请日：1987-12-21
申请人： HITACHI LTD , HITACHI COMMUNICATION SYSTEM
发明人： SAKAKIDA HISAHIRO , SHINADA SHIGEO , KOSUGE SHOJI , NAKAMURA TATSUYA
IPC分类号： H04J3/14
摘要： PURPOSE:To diagnose the function of a device stably and moreover through simple and easy circuit constitution even if jitter exists by controlling a counting operation in a write/read address counter by a prescribed way prior to diagnosis. CONSTITUTION:The phase comparison circuit 18 of a destuff circuit in a diagnosis circuit is operated prior to the diagnosis, and the counting operation of the write/read address counters 16,17 is controlled. Namely, for instance, in a case that the reference phase of the write address counter 16 leads that of the read address counter 17 and the phase difference of them is smaller than a prescribed value (value larger than allowable jitter width), the counting operation of the read address counter 17 is stopped for one bit so as to make the phase difference larger by one bit. Thus, a write address and a read address come to have the phase difference larger than the prescribed difference whichever is made to be a standard, and since a sufficient phase allowance is secured prior to the diagnosis, the function of the device can be diagnosed stably and moreover through the simple and easy circuit constitution even if the jitter is contained in input data.

10. 发明专利

JPH01103039A MONITORING SYSTEM FOR MULTIPLEXER 失效
公开(公告)号：JPH01103039A
公开(公告)日：1989-04-20
申请号：JP25968887
申请日：1987-10-16
申请人： HITACHI LTD
发明人： SHINADA SHIGEO , FUJITA HIROYUKI
IPC分类号： H04J3/14
摘要： PURPOSE:To shorten the time required for deciding a fault after having detected a discrepancy as a result of comparison by shifting to a comparison of a higher order group output signal and a lower order group input signal of a different lower order signal sequence, when a discrepancy is detected as a result of comparison of a higher order group input signal and a lower order group output signal. CONSTITUTION:A first sequence and a lower order group input signal are selected by a selector 49 and a selector 50, respectively, and by signal disconnection information which is sent from a bipolar/unipolar transducer 31 to a control part 57, whether the lower order group input signal is disconnected or not is decided. Unless it is disconnected, a comparison check is executed, and whether a discrepancy exists or not is checked. In such a case, when a discrepancy as a result of comparison is detected for the first time, the check is shifted to the next, second sequence, the comparison check is executed in the same way, and a fault is decided.

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