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1. 发明专利

JPH09107081A SEMICONDUCTOR MEMORY AND SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH09107081A
公开(公告)日：1997-04-22
申请号：JP8991096
申请日：1996-03-21
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： KAJITANI KAZUHIKO , YAMAGUCHI YASUNORI , OSHIMA KAZUYOSHI , YAMAZAKI TAKASHI , MIYAMOTO EIJI , SAKAI YUJI , SAWADA JIRO , ETO JUN , HORIGUCHI SHINJI , IKENAGA SHINICHI , KUMADA ATSUSHI , TSUNOSAKI MANABU , KASAMA YASUHIRO , UDO SHINJI , YOSHIOKA HIROSHI , SAITO HIROMI , TAKANO MITSUHIRO , MORINO MAKOTO , MIYATAKE SHINICHI , MATSUMOTO TETSUO
IPC分类号： G11C11/41 , G11C11/401 , H01L21/82 , H01L21/8242 , H01L27/108
摘要： PROBLEM TO BE SOLVED: To provide a highly integrated device with high speed, by forming a peripheral circuit in first and second regions and providing a plurality of bonding pads on the first region in a zigzag form along the first region for connecting a semiconductor substrate and the outside. SOLUTION: A memory array is formed in a four-sectional area made of cross-shaped areas A to E. Then, a Y-decoder(Ydec) and a Y-select driver (YS driver) are provided according to the upper and lower arrays made in a pair. An X-decoder(Xdec) is put in the area of C and a word line driver (WL driver) is put in the area of D. An address buffer and the like are put in the areas A and B, a common source switch circuit and the like are put in the area of C and D, and an address signal generating circuit for the X-decoder and Y decoder is put in the central area of E. In this way, a large-size semiconductor device can be realized.

2. 发明专利

JPH01145853A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPH01145853A
公开(公告)日：1989-06-07
申请号：JP30319387
申请日：1987-12-02
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： KASAMA YASUHIRO , OSHIMA KAZUYOSHI , TAKANO MITSUHIRO , KOMATSU NOBUO , UDO SHINJI
IPC分类号： H01L27/10 , H01L21/822 , H01L21/8242 , H01L27/04 , H01L27/108
摘要： PURPOSE:To decrease the occurring rate of soft errors in a memory cell mode and a bit line mode, by providing a potential barrier layer beneath the memory cell in a DRAM and beneath a semiconductor region, which is connected to a bit line, and not providing a potential barrier layer beneath a MISFET. CONSTITUTION:A p-type potential barrier layer 4B is constituted at a lower part of a memory cell M. The potential barrier layer 4B is formed beneath the entire surface of the memory cell M, i.e., at the entire surface of a memory cell array MA. The potential barrier layer 4B can be provided at least beneath a data storing capacitor element C of the memory cell M. The potential barrier layer 4B forms a potential barrier against minority carriers, which are generated by incident alpha rays within a semiconductor substrate 1. The potential barrier layer 4B is constituted so as to block the intrusion of the minority carriers into the data storing capacitor element C and so as to decrease the occurring rate of soft errors in a memory cell mode. The potential barrier layer 4B is also constituted so as to increase the charge storing capacity of the data storing capacitor element.

3. 发明专利

JPS6482399A TEST SYSTEM FOR STORED CAPACITY IN SEMICONDUCTOR MEMORY DEVICE 失效
公开(公告)号：JPS6482399A
公开(公告)日：1989-03-28
申请号：JP23724487
申请日：1987-09-24
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： KASAMA YASUHIRO , OSHIMA KAZUYOSHI , KAJITANI KAZUHIKO , YAMAZAKI TAKASHI , TAKANO MITSUHIRO
IPC分类号： G11C11/413 , G11C11/34 , G11C11/401 , G11C29/00 , G11C29/56
摘要： PURPOSE:To detect that a stored capacity does not reach an expected value by leaking the holding charge of a memory cell to be tested in which prescribed data is written to a data line during the non-selection period of a word line and controlling the reading signal level of the holding charge. CONSTITUTION:When the word lines W1-Wn are not selected, a selecting signal S for turning on the selecting MOSFETQ1 of respective memory cells MC is supplied from a testing pad Ptest. The time is shorter than a time for leaking the charge of the required quantity for inverting the holding data of the stored capacity Cs satisfying the expected value of the capacity to the data line DL and longer than a time for leaking the charge of the quantity required for inverting the holding data of the stored capacity Cs satisfying no expected value to the data line DL. Therefore, the data held by the stored capacity Cs satisfying no expected value is inverted to the data of a low level. Thereby, it is detected that the stored capacity does not reach the expected value.

4. 发明专利

JPH03214669A SEMICONDUCTOR STORAGE DEVICE AND REDUNDANT MEMORY REPAIR METHOD 失效
公开(公告)号：JPH03214669A
公开(公告)日：1991-09-19
申请号：JP6584089
申请日：1989-03-20
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： KAJITANI KAZUHIKO , YAMAGUCHI YASUNORI , OSHIMA KAZUYOSHI , YAMAZAKI TAKASHI , MIYAMOTO EIJI , SAKAI YUJI , SAWADA JIRO , ETO JUN , HORIGUCHI SHINJI , IKENAGA SHINICHI , KUMADA ATSUSHI , TSUNOSAKI MANABU , KASAMA YASUHIRO , UDO SHINJI , YOSHIOKA HIROSHI , SAITO HIROMI , TAKANO MITSUHIRO , MORINO MAKOTO , MIYATAKE SHINICHI , MATSUMOTO TETSUO
IPC分类号： G11C11/41 , G11C11/401 , G11C11/407 , G11C11/409 , G11C29/00 , G11C29/04 , H01L21/82 , H01L21/822 , H01L21/8242 , H01L27/04 , H01L27/10 , H01L27/108
摘要： PURPOSE:To attain a high speed and also a large storage capacity by disposing peripheral circuits in cross areas formed of a longitudinal central part and a lateral central part and by disposing memory arrays in four regions divided by the cross areas. CONSTITUTION:In a semiconductor chip or in each of areas divided by the longitudinal center line thereof, peripheral circuits are disposed in cross areas A to E formed of the longitudinal central part and the lateral central part thereof, while memory arrays M are disposed in four regions divided by the cross areas A to E. As the peripheral circuits are disposed in the central parts of the chip or in each of the areas according to this constitution, the maximum transmission path of signals can be shortened to the half of a chip size substantially, and therefore DRAM designed to have a large storage capacity can be made to operate at a high speed.

5. 发明专利

JPH01145851A SEMICONDUCTOR MEMORY DEVICE 失效
公开(公告)号：JPH01145851A
公开(公告)日：1989-06-07
申请号：JP30319487
申请日：1987-12-02
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： YAMAZAKI TAKASHI , OSHIMA KAZUYOSHI , KUMADA ATSUSHI , UDO SHINJI , TAKANO MITSUHIRO
IPC分类号： H01L27/10 , G11C11/409 , H01L21/8242 , H01L27/108
摘要： PURPOSE:To shorten the separating interval between data lines and to improve an integration density, by making the extending direction of complementary data lines agree with the direction of the gate length of a shorting MISFET, and inverting the pattern of a complementary signal in the next stage with respect to the pattern of a preceding complementary signal. CONSTITUTION:In a DRAM, the extending direction of each complementary data line is made to agree with the direction of the gate length of a shorting MISFET QSH. Then, the deviating amount in mask alignment between a connecting part Cont and a gate electrode G of the shorting MISFET QSH is generated in the extending direction of each complementary data line DL. Therefore, the separating interval between the complementary data lines DLs is shortened. With respect to the pattern of the complementary signal of the complementary data line DL, the pattern of the complementary signal of the complementary data line DL at the next stage is inverted. Thus, two data lines (d2 and d3) are made to pass between two connecting parts Cont's between two pieces of the data line (d1 and d4) and two input/output selecting MISFET QYs. Therefore, the separating interval between the data lines can be shortened by the amount of the part, where the separating interval corresponding to the deviating amount in mask alignment is not present.

6. 发明专利

JPS63276783A DYNAMIC RAM 失效
公开(公告)号：JPS63276783A
公开(公告)日：1988-11-15
申请号：JP9986187
申请日：1987-04-24
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： WADA SHOJI , KOMATSU NOBUO , TAKANO MITSUHIRO , MIYATAKE SHINICHI
IPC分类号： G11C11/409 , G11C11/34
摘要： PURPOSE:To speed up operation and to reduce power consumption by executing the necessary control of precharge control signal level by means of a precharge control signal generation circuit. CONSTITUTION:When a timing signal phi turns to H-level associatively with memory access start, the outputs of the NOR gates G1, G2 of the precharge generation circuit comes in L-level, FETs Q59, Q60 turn off, and the Q58 turns off, and a precharge control signal phipc0 comes in half level. Accordingly, by shortcircuiting a complementary data line, the FETs that have been precharged in half level are virtually turned off irrespective of an address consolidation, and the RAM operates at a high speed with the half-level control signal. Subsequently, with the settlement of a row address under a selection causing the signal phi to turn in L-level, the FET Q58 turns on and at the same time the FET Q60 also is made turns on by the L-output of a decoder DEC through the gate G2, hence the signal phipc0 comes in low level. With such a constitution as the above, the operation is speeded up, as well as the power consumption can be reduced because the level shifting of a precharge control signal is in half level.

7. 发明专利

JPH0316259A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH0316259A
公开(公告)日：1991-01-24
申请号：JP14968489
申请日：1989-06-14
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： MIYATAKE SHINICHI , TAKANO MITSUHIRO , WADA SHOJI
IPC分类号： H01L27/10 , H01L21/8242 , H01L27/108
摘要： PURPOSE:To eliminate a parasitic MOS between a guard ring and a capacitor and facilitate prevention of the breakdown of the thin film of the capacitor by a method wherein a predetermined voltage is applied to the guard ring when both a plate voltage level and a substrate voltage level reach a steady state. CONSTITUTION:A monitoring means 13 which monitors a substrate voltage level applied to a semiconductor substrate 1 and a plate voltage level applied to a plate and a judging means 14 which judges whether both the levels reach a steady state or not are provided. Further, a guard ring voltage control means 15 which applies a predetermined voltage to a guard ring 8 when both the levels reach a steady state is provided. Therefore, a voltage is applied to the guard ring 8 when both the plate voltage level and the substrate voltage level reach a steady state. When this constitution, a parasitic MOS which is created between the guard ring and a capacitor when an electric source is closed can be eliminated and the breakdown of the thin film of the capacitor can be avoided.

8. 发明专利

JPH02144963A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND ITS MANUFACTURE 失效
公开(公告)号：JPH02144963A
公开(公告)日：1990-06-04
申请号：JP29812288
申请日：1988-11-28
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： TSUCHIYA OSAMU , KASAMA YASUHIRO , OSHIMA KAZUYOSHI , TAKANO MITSUHIRO , KOMATSU NOBUO , UDO SHINJI , SUWAUCHI NAOKATSU
IPC分类号： H01L27/10 , H01L27/108
摘要： PURPOSE:To enhance a refresh characteristic by a method wherein a high-concentration n-type impurity is introduced into a polycrystalline silicon film, its polycrystalline property is destroyed, an amorphous silicon film is formed, this amorphous silicon film is heat-treated, a single-crystal silicon film is formed and an intermediate conductive film is formed. CONSTITUTION:An intermediate conductive layer 34 is formed at the upper part of an interlayer insulating film 30 in such a way that it is connected to a semiconductor region 31 through a connecting hole 33 formed at the upper part of the other semiconductor region 31 in a MISFET Qs formation region. Then, when a high-concentration n-type impurity is introduced into the polycrystalline silicon film 34, the n-type impurity is diffused to a grain boundary of the polycrystalline silicon film 34; a crystal is destroyed; the polycrystalline silicon film 34 is transformed into an amorphous silicon film 34. Then, the amorphous silicon film 34C is patterned; after that, a heat treatment is executed; then, a grain is formed inside the amorphous silicon film 34 from a part coming into contact with the semiconductor region 31; the intermediate conductive film 34 which has been made to be a single crystal is formed. By this heat-treatment process, the n-type impurity is diffused to the semiconductor region 31; a high-concentration n type semiconductor region 35 is formed. Thereby, it is possible to eliminate an inflection point of the grain boundary in the intermediate conductive film and to prevent a disconnection of a data line.

9. 发明专利

JPH09102592A SEMICONDUCTOR MEMORY 失效
公开(公告)号：JPH09102592A
公开(公告)日：1997-04-15
申请号：JP8991196
申请日：1996-03-21
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： KAJITANI KAZUHIKO , YAMAGUCHI YASUNORI , OSHIMA KAZUYOSHI , YAMAZAKI TAKASHI , MIYAMOTO EIJI , SAKAI YUJI , SAWADA JIRO , ETO JUN , HORIGUCHI SHINJI , IKENAGA SHINICHI , KUMADA ATSUSHI , TSUNOSAKI MANABU , KASAMA YASUHIRO , UDO SHINJI , YOSHIOKA HIROSHI , SAITO HIROMI , TAKANO MITSUHIRO , MORINO MAKOTO , MIYATAKE SHINICHI , MATSUMOTO TETSUO
IPC分类号： G11C11/401 , H01L21/82 , H01L21/8242 , H01L27/108
摘要： PROBLEM TO BE SOLVED: To increase the memory capacity or large scale integration by providing a step buffer area made of a dummy conductor layer between a memory array and a peripheral circuit by sing a plurality of dynamic memory cells having a laminated capacitor as a memory cell formed in the memory array. SOLUTION: A memory chip has memory arrays M divided into four by cross areas made of areas A to E. The arrays M divided into the four are disposed by extending a word line in the lateral direction, and disposed by extending a data line (bit line or digit line) in a vertical direction. A step buffer area made of a dummy wiring layer is provided between the arrays M and the peripheral circuit. A guard ring is disposed under the step buffer area to stabilize the characteristics.

10. 发明专利

JPH04258161A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPH04258161A
公开(公告)日：1992-09-14
申请号：JP4095491
申请日：1991-02-12
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： ISHII KYOKO , MIYATAKE SHINICHI , TAKAHASHI TSUTOMU , UDO SHINJI , YOSHIOKA HIROSHI , TAKANO MITSUHIRO , MORINO MAKOTO
IPC分类号： H01L21/822 , G11C5/14 , G11C7/06 , G11C8/12 , G11C11/401 , G11C11/407 , H01L21/8242 , H01L27/04 , H01L27/10 , H01L27/108
摘要： PURPOSE:To prevent an irregularity in a leakage current of a memory cell due to a reduction in a power source noise and an irregularity in heat generation by providing a plurality of internal step-down circuits for forming an operating voltage of a sense amplifier upon reception of a power source voltage from an exterior corresponding to memory blocks one by one. CONSTITUTION:An X decoder 3 interprets an address signal having 9 bits X0-X9, and selects one word line. When an X address signal is fetched in synchronizm with a row address strobe signal RAS, an X series is selected. The word lines are selected one by one in each memory block, and one memory mat as indicated by a shade and one sense amplifier are operated. Internal step-down circuits 8 each for forming an operating voltage are respectively provided in the blocks corresponding to selection of the word line and dispersing operation of the amplifier. Thus, it prevents generation of noise of a high level due to flow of a large current concentrically to special wirings.

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