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1. 发明专利

JPH09102592A SEMICONDUCTOR MEMORY 失效
公开(公告)号：JPH09102592A
公开(公告)日：1997-04-15
申请号：JP8991196
申请日：1996-03-21
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： KAJITANI KAZUHIKO , YAMAGUCHI YASUNORI , OSHIMA KAZUYOSHI , YAMAZAKI TAKASHI , MIYAMOTO EIJI , SAKAI YUJI , SAWADA JIRO , ETO JUN , HORIGUCHI SHINJI , IKENAGA SHINICHI , KUMADA ATSUSHI , TSUNOSAKI MANABU , KASAMA YASUHIRO , UDO SHINJI , YOSHIOKA HIROSHI , SAITO HIROMI , TAKANO MITSUHIRO , MORINO MAKOTO , MIYATAKE SHINICHI , MATSUMOTO TETSUO
IPC分类号： G11C11/401 , H01L21/82 , H01L21/8242 , H01L27/108
摘要： PROBLEM TO BE SOLVED: To increase the memory capacity or large scale integration by providing a step buffer area made of a dummy conductor layer between a memory array and a peripheral circuit by sing a plurality of dynamic memory cells having a laminated capacitor as a memory cell formed in the memory array. SOLUTION: A memory chip has memory arrays M divided into four by cross areas made of areas A to E. The arrays M divided into the four are disposed by extending a word line in the lateral direction, and disposed by extending a data line (bit line or digit line) in a vertical direction. A step buffer area made of a dummy wiring layer is provided between the arrays M and the peripheral circuit. A guard ring is disposed under the step buffer area to stabilize the characteristics.

2. 发明专利

JPS63261598A SEMICONDUCTOR MEMORY 失效
公开(公告)号：JPS63261598A
公开(公告)日：1988-10-28
申请号：JP9517987
申请日：1987-04-20
申请人： HITACHI LTD , HITACHI VLSI ENG , HITACHI DEVICE ENG
发明人： YAMAGUCHI YASUNORI , YOSHIDA HIROHIKO , NEI MASAMI , ISHIHARA MASAMICHI , YAMAMOTO YUKIO
IPC分类号： G11C11/41 , G11C11/34 , G11C11/401
摘要： PURPOSE:To simplify the constitution of a circuit by using a common column decoder circuit to produce a selecting signal for random input/output and an initial address for serial input/output respectively. CONSTITUTION:A signal route is provided for parallel transmission of signals to the data lines of memory arrays M-ARY0 and M-ARY1 as well as to latch circuits DFF0 and DFF1. While a switch route functions for connecting the circuits DFF0 and DFF1 to a common data line for serial input/output by means of a selecting signal produced by a shift register SR. At the same time, the output signal of a column decoder circuit C-DCR is supplied to each bit of the register SR as the initial value. Thus the circuit C-DCR is used in common for random input/output and serial input/output. As a result, both random input/ output and serial input/output are possible and at the same time the relevant circuit constitution can be simplified.

3. 发明专利

JPS63239678A SEMICONDUCTOR STORAGE DEVICE 失效
公开(公告)号：JPS63239678A
公开(公告)日：1988-10-05
申请号：JP7150887
申请日：1987-03-27
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： MIYAKE JUN , KAWAGUCHI HITOSHI , YAMAGUCHI YASUNORI , NAGASHIMA YASUSHI , YOSHIDA MASAHIRO , YUGAWA YOSUKE , SAEKI TETSUYA , OKADA TERUTAKA , MORINO MAKOTO
IPC分类号： G11C11/401 , G11C11/34
摘要： PURPOSE:To execute a data transfer cycle at an optional timing and to increase a data transfer rate of a system by providing a dual port memory with two registers and using these registers alternately in accordance with a prescribed control procedure. CONSTITUTION:The titled device is provided with two data registers DRA1, DRB1 whose respective bits correspond to plural complementary data lines D0, D0-Dn, Dn constituting a memory array M-ARY1. During the serial I/O operation of memory data through one data register DRA1, the memory data can be transferred in parallel through the other data register DRB1 at a comparatively optional timing. Consequently, the serial I/O operation can be continuously repeated at a comparatively rapid data transfer rate and a processor or the like arranged on the outside of the dual port memory can be simplified.

4. 发明专利

JPH03214669A SEMICONDUCTOR STORAGE DEVICE AND REDUNDANT MEMORY REPAIR METHOD 失效
公开(公告)号：JPH03214669A
公开(公告)日：1991-09-19
申请号：JP6584089
申请日：1989-03-20
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： KAJITANI KAZUHIKO , YAMAGUCHI YASUNORI , OSHIMA KAZUYOSHI , YAMAZAKI TAKASHI , MIYAMOTO EIJI , SAKAI YUJI , SAWADA JIRO , ETO JUN , HORIGUCHI SHINJI , IKENAGA SHINICHI , KUMADA ATSUSHI , TSUNOSAKI MANABU , KASAMA YASUHIRO , UDO SHINJI , YOSHIOKA HIROSHI , SAITO HIROMI , TAKANO MITSUHIRO , MORINO MAKOTO , MIYATAKE SHINICHI , MATSUMOTO TETSUO
IPC分类号： G11C11/41 , G11C11/401 , G11C11/407 , G11C11/409 , G11C29/00 , G11C29/04 , H01L21/82 , H01L21/822 , H01L21/8242 , H01L27/04 , H01L27/10 , H01L27/108
摘要： PURPOSE:To attain a high speed and also a large storage capacity by disposing peripheral circuits in cross areas formed of a longitudinal central part and a lateral central part and by disposing memory arrays in four regions divided by the cross areas. CONSTITUTION:In a semiconductor chip or in each of areas divided by the longitudinal center line thereof, peripheral circuits are disposed in cross areas A to E formed of the longitudinal central part and the lateral central part thereof, while memory arrays M are disposed in four regions divided by the cross areas A to E. As the peripheral circuits are disposed in the central parts of the chip or in each of the areas according to this constitution, the maximum transmission path of signals can be shortened to the half of a chip size substantially, and therefore DRAM designed to have a large storage capacity can be made to operate at a high speed.

5. 发明专利

JPH1055059A PRODUCTION OF PHOTOMASK AND PRODUCTION OF SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPH1055059A
公开(公告)日：1998-02-24
申请号：JP21071396
申请日：1996-08-09
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： SHIRAI SEIICHIRO , YAMAGUCHI YASUNORI , ONOZUKA TOSHIHIKO , HOTTA SHOJI , NOMURA KEIKO , MORITA MASAYUKI
IPC分类号： G03F1/68 , G03F1/70 , H01L21/027 , G03F1/08
摘要： PROBLEM TO BE SOLVED: To improve the dimensional accuracy of semiconductor integrated circuit patterns by forming data for plotting in accordance with the design data of the mask patterns of corrected first pattern layers and forming light shielding patterns on the mask substrate in accordance with the data for plotting. SOLUTION: The first pattern layer to be corrected and the second pattern layer to be a reference are selected on a pattern data correction device. The design data of the mask patterns of a contact hole layer and the design data of the mask patterns of a gate electrode layer are automatically extracted. Next, the distances L', L" between the contact hole CN9 and the gate electrodes FG2 , FG3 are respectively automatically calculated from the design data. Next, the contact holes CN1 to CN12 constituting the contact hole layer are automatically classified in accordance with the reference set in accordance with these distances and the correction of the pattern sizes on the design data are automatically executed by each of the classified contact holes.

6. 发明专利

JPH09107081A SEMICONDUCTOR MEMORY AND SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH09107081A
公开(公告)日：1997-04-22
申请号：JP8991096
申请日：1996-03-21
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： KAJITANI KAZUHIKO , YAMAGUCHI YASUNORI , OSHIMA KAZUYOSHI , YAMAZAKI TAKASHI , MIYAMOTO EIJI , SAKAI YUJI , SAWADA JIRO , ETO JUN , HORIGUCHI SHINJI , IKENAGA SHINICHI , KUMADA ATSUSHI , TSUNOSAKI MANABU , KASAMA YASUHIRO , UDO SHINJI , YOSHIOKA HIROSHI , SAITO HIROMI , TAKANO MITSUHIRO , MORINO MAKOTO , MIYATAKE SHINICHI , MATSUMOTO TETSUO
IPC分类号： G11C11/41 , G11C11/401 , H01L21/82 , H01L21/8242 , H01L27/108
摘要： PROBLEM TO BE SOLVED: To provide a highly integrated device with high speed, by forming a peripheral circuit in first and second regions and providing a plurality of bonding pads on the first region in a zigzag form along the first region for connecting a semiconductor substrate and the outside. SOLUTION: A memory array is formed in a four-sectional area made of cross-shaped areas A to E. Then, a Y-decoder(Ydec) and a Y-select driver (YS driver) are provided according to the upper and lower arrays made in a pair. An X-decoder(Xdec) is put in the area of C and a word line driver (WL driver) is put in the area of D. An address buffer and the like are put in the areas A and B, a common source switch circuit and the like are put in the area of C and D, and an address signal generating circuit for the X-decoder and Y decoder is put in the central area of E. In this way, a large-size semiconductor device can be realized.

7. 发明专利

JPS62208491A SEMICONDUCTOR STORAGE DEVICE 失效
公开(公告)号：JPS62208491A
公开(公告)日：1987-09-12
申请号：JP4840386
申请日：1986-03-07
申请人： HITACHI LTD , HITACHI VLSI ENG , HITACHI DEVICE ENG
发明人： YAMAGUCHI YASUNORI , YOSHIDA HIROHIKO , NEI MASAMI , ISHIHARA MASAMICHI , YAMAMOTO YUKIO
IPC分类号： G11C7/00 , G11C7/10 , G11C8/00 , G11C8/04 , G11C8/16 , G11C11/401
摘要： PURPOSE:To simplify a circuit and to improve a function by setting an initial value based on the output signal of a column decoder circuit and including a shift register forming the selection signal of a switch circuit for serial I/O due to the shift action of the initial value. CONSTITUTION:A complementary data line in a memory arrayes M-ARY0 and MARY1 connected to common data lines CD0 and CD1 through column switch circuits C-SW0 and C-SW1. A decode signal included in a column address signal supplied from the column decoder C-DCR in a serial transfer mode initializes the shift register SR (logic '1'), which executes a shift action. In that case signals of the M-ARY0 and M-ARY1 are outputted alternately in serial, and the common data liens CD0 and CD1 are linked to a random I/O output terminal D through a random I/O output circuit I/O and to a serial I/O output terminal Ds through a serial I/O circuit SIO. Thus a simple circuit can have a random I/O function and a serial I/O function.

8. 发明专利

JPH08148643A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE, MANUFACTURE THEREOF, AND RESIN MOLDING DIE THEREFOR 失效
公开(公告)号：JPH08148643A
公开(公告)日：1996-06-07
申请号：JP28572794
申请日：1994-11-18
申请人： HITACHI LTD , HITACHI VLSI ENG , HITACHI HOKKAI SEMICONDUCTOR
发明人： NISHIZAWA HIROTAKA , MIURA TOMOYOSHI , ANJO ICHIRO , YAMADA TOSHIO , SEKINE YASUSHI , OBARA TETSUJI , HANABUSA YOSHIAKI , SUGANO TOSHIO , YAMAGUCHI YASUNORI , SAWADA JIRO , YAMAMURA MASAHIRO , ISHIHARA MASAMICHI , MORITA SADAO , ARAKI TAKASHI , TAKEURA SHINOBU , FUDA MUTSUO , KASAI NORIHIKO , GOTO MASAKATSU
IPC分类号： H01L25/18 , H01L21/56 , H01L25/065 , H01L25/07
摘要： PURPOSE: To provide a miniature, high-performance multichip module and a manufacturing technique therefor. CONSTITUTION: Lead frames mounted with a semiconductor chip are stacked up to a specified number of layers, and sealed in a lump with resin to form a package 2. The obtained package 2 is placed on a mother socket 3. The outer leads 6 of the lead frames, led out of the side of the package 2, are electrically connected with the leads 7 of the mother socket that extend in the direction orthogonal to the direction of the extension of the outer leads 6, and a DRAM module 1 is thereby formed.

9. 发明专利

JPH08263982A SEMICONDUCTOR STORAGE 失效
公开(公告)号：JPH08263982A
公开(公告)日：1996-10-11
申请号：JP1251596
申请日：1996-01-29
申请人： HITACHI LTD
发明人： YAMAGUCHI YASUNORI , MIYAKE JUN
IPC分类号： G11C11/401 , G11C7/00 , G11C7/10 , H04N5/907
摘要： PURPOSE: To indicate and form a new operation mode by judging the level of a specified control signal supplied prior to a substantial chip selection signal and thereby forming a signal for establishing a function signal. CONSTITUTION: The signals of complementary data lines in a memory array are transferred in parallel to each bit of the shift registers composed of four sets in total each through switching MOSFET Q10, Q11, etc. These transistors, Q10, Q11, are controlled by a timing signal ϕS, supplied in common to their gates to control the transfer timing of signals. Thus the above device is provided with a function of reading the memory information corresponding to one word in the memory array in parallel and sending four-bit signals serially from the shift registers SR of four sets in total to an external terminal Ds. Such function does not increase external terminals, but generates graphic data of red, blue, green and luminance of color images to be displayed in synchronization with the raster scan timing of a CRT.

10. 发明专利

JPH06267277A SEMICONDUCTOR MEMORY DEVICE 失效
公开(公告)号：JPH06267277A
公开(公告)日：1994-09-22
申请号：JP8145793
申请日：1993-03-16
申请人： HITACHI LTD
发明人： YAMAGUCHI YASUNORI
IPC分类号： G11C11/41 , G11C11/401
摘要： PURPOSE:To reduce a chip area of a dual port memory, etc., provided with a serial access port and to reduce its cost. CONSTITUTION:In the dual port memory, etc., provided with the serial access port, a memory array is divided and arranged as e.g. eight pieces of memory arrays MARY0-MARY7 in the prolonging direction of a bit line. Further, sense amplifiers SA0-SA3 and data registers DR0-DR4 are arranged alternately between these memory arrays, and these sense amplifiers and data resisters are shared by a pair of memory arrays arranged on whose both sides. Then, the required number of installation of the sense amplifiers and the data registers in the dual port memory, etc., are reduced while utilizing the merit of a shared sense system. Thus, the chip area of the dual port memory, etc., is reduced, and its cost is reduced.

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