专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明专利

JPH07312365A METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH07312365A
公开(公告)日：1995-11-28
申请号：JP10147494
申请日：1994-05-17
申请人： HITACHI LTD
发明人： MATSUI YUICHI , MIKI HIROSHI , HIRAYAMA MISUZU , NAKADA MASAYUKI , NAKAMURA YOSHITAKA , IZAWA MASARU , OJI YUZURU
IPC分类号： H01L27/04 , H01L21/205 , H01L21/316 , H01L21/822 , H01L21/8242 , H01L27/10 , H01L27/108
摘要： PURPOSE:To uniformly accumulate an insulation film on a lower electrode of a material which is remarkably uneven on a surface without reducing specific inductive capacity by a method wherein other elements have beforehand been added in a metal film and are diffused up to an insulation film surface in an insulation film accumulation. CONSTITUTION:There exist a recess and a projection of about 20nm at max due to a crystal grain boundary on a W film surface. In the prior art (b), it is understood that a film thickness is thinned to about half in a corner part on the bottom of the recess and the projection on a surface of a W crystal grain 3. As a Ta2O5 film 2 is increased promptly leak current when the film thickness is thinned, a large leak current flows out from a portion where the film thickness is thin locally. However, in this embodiment (a), a curvature of the surface of Ta2O5 film 2 can be made the same as or higher than that of the corner part on the bottom of the recess and the projection of a W crystal grain 1 (to which Si is added), and the leak current can be reduced more than the prior art. By controlling the annexing amount of Si, absorption probability of the Ta2O5 film 2 can be reduced without decreasing specific inductive capacity.

2. 发明专利

JPS60149149A MANUFACTURE OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS60149149A
公开(公告)日：1985-08-06
申请号：JP481984
申请日：1984-01-17
申请人： HITACHI LTD
发明人： TADAKI YOSHITAKA , NAKADA MASAYUKI , MOTOYOSHI MAKOTO , SAKAI YOSHIO , KAWAMOTO YOSHIFUMI
IPC分类号： H01L27/08 , H01L21/316 , H01L21/76
摘要： PURPOSE:To provide an isolation groove in self-alignment by a method wherein a well pattern is made of an insulation film or the like, the side surface of which pattern is coated with an organic film, and an Si substrate is deeply etched only at the region of the side surface. CONSTITUTION:An SiO2 9, an Si3N4 8, and a CVDSiO2 7 are laminated on the Si substrate 6, and the film 7 is processed with a resist mask 10; then, a wall of organic film 11 is formed on the side surfaces of the films 10 and 7. The film 8 is etch-removed after implantation of phosphorus ions 12 with the films 10 and 11 as a mask. The masks 10 and 11 are removed, and an SiO2 13 is produced by heat treatment. After implantation of boron ions 14 with the SiO2's 7 and 13 as a mask, the groove 15 is provided by etching the films 8' and 9 and the substrate 6, and the films 7 and 13 are removed. Next, the whole is covered with an SiO2 16, and boron ions 17 are implanted after removal of an Si3N4 8''; then, a P-well 23 and an N-well 24 are formed by annealing. An Si3N4 mask 18 is formed with a photo resist 20, and the surface inversion of the P-well 23 is prevented by implanting boron ions 19. The resist 20 is removed and an SiO2 21 is formed, and the groove is filled with poly Si or SiO2; beside, an Si3N4 18 is removed, resulting in the completion of a CMOS. This construction enables the isolation groove for latch-up prevention to be provided in self-alignment.

3. 发明专利

JPH1011977A SEMICONDUCTOR STORAGE DEVICE 失效
公开(公告)号：JPH1011977A
公开(公告)日：1998-01-16
申请号：JP16555496
申请日：1996-06-26
申请人： HITACHI LTD
发明人： OYU SHIZUNORI , KAWAMOTO YOSHIFUMI , IIJIMA SHINPEI , NAKADA MASAYUKI , HIRAYAMA MISUZU , SUGAWARA YASUHIRO , TANAKA TOSHIHIRO
IPC分类号： G11C14/00 , G11C11/22 , H01L21/8242 , H01L27/108
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor storage device exhibiting no deterioration in memory capability and to realize reliability and stability of a dielectric film by applying an electric potential to the dielectric film of a capacitor in the semiconductor memory device so as to reduce charges to be captured in the dielectric film. SOLUTION: Prior to a refresh operation, in order to pre-charge data lines 17a and 17b to 1/2Vcc, a PC signal and an RSL signal are transmitted to circuits 4a and 4b which perform pre-charging. In the circuits 4a and 4b, 1/2Vcc are applied to the data lines 17a and 17b. Then, a timing controller TC operates after an electric potential of the data lines 17 reaches Vss or Vcc by operations of a sense amplifier 2 or after the lapse of a predetermined period of time which has been set by assuming that the potential is amplified to the level close to Vss or Vcc during that period. Thus, a MISFET 26 in an information inverting portion turns off to set the data lines 17a and 17b in an electrically open condition. Information inverted with respect to the information stored in a memory cell is preserved on a data line in a memory cell region and a data line connected to the sense amplifier.

4. 发明专利

JPH07183395A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH07183395A
公开(公告)日：1995-07-21
申请号：JP32370193
申请日：1993-12-22
申请人： HITACHI LTD
发明人： KAGA TORU , YADORI SHOJI , NAKADA MASAYUKI , OJI YUZURU , KURE TOKUO
IPC分类号： H01L29/43 , H01L21/28 , H01L21/822 , H01L21/8242 , H01L27/04 , H01L27/10 , H01L27/108
摘要： PURPOSE:To reduce current flowing through an insulating film and to enhance the dielectric strength by forming a laminate of a plurality of insulating films on a silicon layer and setting the band gap of lowermost SiO2 insulating film wider than that of a Ta2O5 insulating film formed thereon CONSTITUTION:A P-type impurity layer 102 is formed on the surface of an n-type silicon substrate and SiO2 is deposited thereon. p-type polysilicon 104 deposited on the SiO2 while containing boron by 10 /cm is connected with the p-type impurity layer 102 through an opening made through the Sin. A two layer insulation film 105 of SiO2(lower layer) and Ta2O5 (upper layer) is then deposited on the p-type polysilicon 104. Since p-type polysilicon is employed for the underlying electrode, the barrier height of SiO2 is increased upon application of a positive voltage to the upper electrode. Consequently, the tunneling probability of SiO2 layer is decreased and when a negative voltage is applied to the upper electrode, the work function of upper electrode increases thus decreasing the electric field in the Ta2O5 layer.

5. 发明专利

JPH04320036A SEMICONDUCTOR DEVICE AND ITS MANUFACTURE 失效
公开(公告)号：JPH04320036A
公开(公告)日：1992-11-10
申请号：JP8654791
申请日：1991-04-18
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： SHIMIZU AKIHIRO , YAMANAKA TOSHIAKI , JINRIKI HIROSHI , NAKADA MASAYUKI , HASHIMOTO NAOTAKA , HASHIMOTO KOJI
IPC分类号： H01L21/314 , H01L21/336 , H01L21/8242 , H01L21/8244 , H01L27/10 , H01L27/108 , H01L27/11 , H01L29/78 , H01L29/786
摘要： PURPOSE:To provide a semiconductor device having MISFETs suitable for high reliability and high current driving capacity. CONSTITUTION:A source/drain has an LDD structure provided with a high- dielectric side wall spacer 6 in a vicinity of the gate electrode side wall on top of a low-doped diffusion layer 2, and with another tunneling thin film insulating film 7 between the side wall spacer and the diffusion layer 2. A gate fringe field effect to the diffusion layer 2 is improved, and hot carrier deterioration special to the LDD structure is made hard to occur; therefore, improvement in reliability of field relaxation and improvement in current driving power can be realized simultaneously.

6. 发明专利

JPS60249345A SEMICONDUCTOR DEVICE AND MANUFACTURE THEREOF 失效
公开(公告)号：JPS60249345A
公开(公告)日：1985-12-10
申请号：JP10451784
申请日：1984-05-25
申请人： HITACHI LTD
发明人： KAWAMOTO YOSHIFUMI , NAKADA MASAYUKI
IPC分类号： H01L21/76 , H01L21/763
摘要： PURPOSE:To obtain good performance of element isolation without crystal defects in a semiconductor substrate by advancing the initial oxidation outside a groove by a method wherein a semiconductor or conductor larger than the upper part of the groove is formed over the groove. CONSTITUTION:The groove 102 is formed in a P type Si substrate 101. A double- layer film 103 of SiO2 and Si3N4 is formed on the surface of the Si substrate, and the first polycrystalline Si 104 and the second polycrystalline Si 105 are left at the groove section. The multilayer film 103 is left in the active region A, and boron is ion-implanted after the multilayer film of the element isolation region B is removed by etching. Next, using the multilayer film 103 as a mask, the polycrystalline Si 105, part of the polycrystalline Si 104 in the groove, and the surface of the substrate 101 are oxidized, resulting in the formation of an SiO2 film 106. Thereafter, the exposed multilayer film 103 of the active region A is removed, and a gate insulation film 107, a gate electrode 108, N type impurity layers 109 and 110 of high concentration, and a phosphosilicate glass 111 are formed. A contact hole is bored, and an aluminum electrode 112 is formed; accordingly, a MOS type transistor is produced. This manner eliminates the generation of crystal defects accompanying the oxidation of the SiO2 film 106.

7. 发明专利

JPS6080244A ELEMENT ISOLATION METHOD OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS6080244A
公开(公告)日：1985-05-08
申请号：JP18687583
申请日：1983-10-07
申请人： HITACHI LTD
发明人： KAWAMOTO YOSHIFUMI , KURE TOKUO , NAKADA MASAYUKI , OKAZAKI SHINJI
IPC分类号： H01L21/76 , H01L21/762
摘要： PURPOSE:To reduce stress to a substrate and eliminate generation of crystal defect by vertically providing many pole-like projections consisting of substrate within a groove without filling the groove provided in the isolation region with an oxide at one time on the occasion of insulating and isolating a pluality of semiconductor elements formed on the semiconductor substrate but instead changing it to an oxide in expanded volume by the heat processing and filling the groove with the oxide. CONSTITUTION:On the occasion of providing element isolation regions between the active regions 208 formed on the semiconductor substrate 204, the SiO2 film 205 and Si3N4 film 206 are stacked and deposited on the entire part of substrate. Next, the active region 208 is covered with a resist film 207 and a groove 213 for element isolation is formed by the etching. In this case, the groove 213 is not provided entirely and many pole-like projections 210 consisting of substrate 204 having the films 206 and 205 at the surface vertically remain herein. Thereafter, the projections 210 is changed to oxide in expanded volume by the heat processing and simultaneously the oxide directly connected thereto is generated at the bottom surface. After this area is buried with the oxide 212, the films 206 and 205 are removed.

8. 发明专利

JPH1126712A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE, METHOD, AND DEVICE FOR MANUFACTURING THE SAME 失效
公开(公告)号：JPH1126712A
公开(公告)日：1999-01-29
申请号：JP17268497
申请日：1997-06-30
申请人： HITACHI LTD
发明人： IIJIMA SHINPEI , SUGAWARA YASUHIRO , OYU SHIZUNORI , ASANO ISAMU , TAMARU TAKESHI , KUNITOMO MASATO , NAKADA MASAYUKI , OJI YUZURU
IPC分类号： H01L21/8242 , H01L27/108
摘要： PROBLEM TO BE SOLVED: To reduce a leakage current of an information storage capacitance element. SOLUTION: A lower electrode 60 constituting an information storage capacitance element C is made of a polycrystal silicon film formed by solid phase crystallization of a deposited amorphous silicon film. A CMP method is used for working the lower electrode 60. A capacitance insulating film 61 constituting the information storage capacitance element C is made of a silicon nitride film and a polycrystal tantalum oxide film. The silicon nitride film is formed by a CVD method. The tantalum oxide film is formed by depositing an amorphous tantalum oxide film by a CVD method and then thermally treating the tantalum oxide film in an oxidative atmosphere. In addition, an upper electrode 62 constituting the information storage capacitance element C is made of a titanium nitride film formed by a CVD method. The intrinsic stress of the titanium nitride film is caused to be not more than 1 GPa.

9. 发明专利

JPH07169917A MANUFACTURE OF CAPACITOR 失效
公开(公告)号：JPH07169917A
公开(公告)日：1995-07-04
申请号：JP31626493
申请日：1993-12-16
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： HIRAYAMA MISUZU , NAKADA MASAYUKI , IIJIMA SHINPEI , YOKOYAMA NATSUKI , OJI YUZURU , KISU TERUAKI , MATSUI YUICHI
IPC分类号： H01L27/04 , H01L21/20 , H01L21/26 , H01L21/316 , H01L21/324 , H01L21/822 , H01L21/8242 , H01L27/108
摘要： PURPOSE:To form a high capacity and high pressure resistant capacitor by using a high dielectric oxidative tantalum film. CONSTITUTION:After an oxidative tantalum layer 5 is formed on a first electrode extending on a first insulation film formed on a silicon substrate 1, first heat treatment is carried out at temperatures of 600 deg.C or above and less than 750 deg.C under an oxygen or oxygen dinitride atmosphere or oxygen or oxygen dinitride atmosphere diluted with argon or nitrogen at the concentration of 0.1% and above. Then, the second heat treatment is carried out at a higher temperature than the first heat treatment, and under an inactive atmosphere, such as argon or nitrogen or oxygen or oxygen dinitride atmosphere diluted below 0.1% with argon or nitrogen, thereby crystallizing the oxidative layer 5. Then, the second electrode 6 is formed on the oxidative tantalum layer, thereby producing a capacitor.

10. 发明专利

JPH0374878A MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH0374878A
公开(公告)日：1991-03-29
申请号：JP21007189
申请日：1989-08-16
申请人： HITACHI LTD
发明人： JINRIKI HIROSHI , NAKADA MASAYUKI , MUKAI KIICHIRO
IPC分类号： H01L29/78 , H01L21/8242 , H01L27/108 , H01L29/72
摘要： PURPOSE:To obtain an IGFET using a transition metal oxide film especially for a gate insulation film by penetrating the gate insulation film without performing light oxidation and by implanting ion. CONSTITUTION:An SiO2 is provided on the surface of a p-type Si substrate 1 for implanting a channel of BF2. The SiO2 film is eliminated and a tantalum pentoxide 2 is sputtered. Treatment is performed within dry O2 at 800 deg.C and an SiO2 film 3 is formed between the substrate 1 and the tantalum pentoxide 2. Then, a W film 4 is sputtered and a PSG 5 is superposed. The PSG 5 is subjected to patterning and the W film 4 is machined with the PSG 5 as a mask. Then, As ion is implanted, thermal treatment is performed within N2 for producing an n layer 6, and a drain layer is provided in self-aligned manner to a W gate pattern. Further, an interlayer insulation film 7 is superposed and a wiring metal film 8 is provided for completing an FET. With this method, it is possible to form an IGFET without performing light oxidation even if a material with an extremely rapid diffusion of an oxidation seed such as tantalum pentoxide is used as a gate insulation film.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式