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1. 发明专利

JP2509173B2 失效
公开(公告)号：JP2509173B2
公开(公告)日：1996-06-19
申请号：JP2167385
申请日：1985-02-08
申请人： HITACHI LTD
发明人： IKEDA SHUJI , MOTOYOSHI MAKOTO
IPC分类号： H01L21/8234 , H01L21/22 , H01L21/265 , H01L21/336 , H01L21/8238 , H01L27/088 , H01L27/092 , H01L29/78

2. 发明专利

JPH0763403A AIR CONDITIONER 失效
公开(公告)号：JPH0763403A
公开(公告)日：1995-03-10
申请号：JP21548693
申请日：1993-08-31
申请人： HITACHI LTD
发明人： SHONO HIROYUKI , INOUE TORU , TERAUCHI HIDEKI , MOTOYOSHI MAKOTO
IPC分类号： F24F11/02
摘要： PURPOSE:To reduce the size of an indoor control circuit by a method wherein an indoor device and an outdoor device are provided with a modulating or demodulating circuit, and a communication between an indoor control circuit and an outdoor control circuit is carried out by being overlapped to a connection line for supplying DC power source. CONSTITUTION:A commercial power source 9 is received by an indoor device 13 and the electrical power is transmitted to an outdoor device 14 through a connection line 18. A DC power source circuit 12 arranged in the outdoor device 14 supplies a DC power source to an indoor control circuit 10 through a connection line 19. Modulating or demodulating circuits 17-a, 17-b connected to the connection line 19 for supplying the DC power source are installed in the indoor device 13 and the outdoor device 14. The indoor control circuit 10 and an outdoor control circuit 11 are communicated from each other through the connection line 19 via the modulating or demodulating circuits 17a, 17b. Accordingly, even if the commercial power source 9 is received at the indoor device 13 and there is provided a connection line for transmitting the electrical power from the indoor device 13 to the outdoor device 14, the connection line performing a communication with the connection line 19 for supplying the DC current can be commonly used, resulting in that the number of connection lines is not increased. With such an arrangement as above, it is possible to provide a small-sized indoor control circuit 10.

3. 发明专利

JPH02172273A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPH02172273A
公开(公告)日：1990-07-03
申请号：JP32582588
申请日：1988-12-26
申请人： HITACHI LTD
发明人： MEGURO SATOSHI , UCHIBORI KIYOBUMI , SUZUKI NORIO , MOTOYOSHI MAKOTO , KOIKE ATSUYOSHI , YAMANAKA TOSHIAKI , SAKAI YOSHIO , HONJO SHIGERU , MINATO OSAMU , KAGA TORU , HASHIMOTO NAOTAKA , HASHIMOTO KOJI
IPC分类号： H01L27/01 , H01L21/8244 , H01L27/00 , H01L27/11
摘要： PURPOSE:To increase the freedom of memory cell layout by arranging the gate electrode of an MISFET for load on the upper part of the gate electrode of an MISFET for driving, and arranging source drain and channel regions of the MISFET for load on the upper part of the gate electrode of the MISFET for load. CONSTITUTION:In the memory cell of a CMOS type SRAM MISFET's Qp1, Qp2 for load are arranged on the upper part of MISFET's Qd1, QD2 for driving. The MOSFET's for load have gate electrodes 34 different from gate electrodes 27 of the MISFET's for driving. As a result, source.drain and channel regions 37A-37C of the MISFET's Qp1, Qp2 for load can be laid out almost without restrictions to the gate electrodes 27 of the MISFET's Qd1, Qd2 for driving. Thereby the freedom of memory cell layout can be increased.

4. 发明专利

JPH01184949A MANUFACTURE OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH01184949A
公开(公告)日：1989-07-24
申请号：JP832188
申请日：1988-01-20
申请人： HITACHI LTD
发明人： TAKAHASHI MASATO , MOTOYOSHI MAKOTO
IPC分类号： H01L29/78 , H01L21/336 , H01L21/8244 , H01L27/10 , H01L27/11
摘要： PURPOSE:To make it possible to prevent reliably the deterioration of the breakdown strength characteristics of a gate and the variability of the electrical characteristics of the gate by a method wherein, after a gate lower layer material is adhered on the surface of a gate insulating film, a contact part is formed, then a gate upper layer material is adhered. CONSTITUTION:Diffused regions 2 and 3, which show a conductivity different from each other, are formed in a substrate 1 consisting of an Si single crystal and thereafter, a field insulating film 5 for element isolation and a gate insulating film 6 are formed. Then, after a poly Si film 7, which is used as a gate lower layer material, is adhered on the whole surface of the substrate 1 by a CVD method, a prescribed place is perforated by etching using a photoresist as a mask to form a contact part 8. After that, a gate 11 of a two-layer structure, which is constituted of a gate lower layer 7a consisting of poly Si and a gate upper layer 10a consisting of tungsten silicide, is formed. Thereby, such a trouble that the film 6 is contaminated by the photoresist is dissolved and the deterioration of the breakdown strength characteristics of the gate 11 and the variability of the electrical characteristics of the gate 11 can be reliably prevented.

5. 发明专利

JPS6342165A SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURE THEREOF 失效
公开(公告)号：JPS6342165A
公开(公告)日：1988-02-23
申请号：JP18507786
申请日：1986-08-08
申请人： HITACHI LTD
发明人： IKEDA SHUJI , MEGURO SATOSHI , MOTOYOSHI MAKOTO , MINATO OSAMU
IPC分类号： H01L27/11 , H01L21/8244 , H01L27/10
摘要： PURPOSE:To omit a mask forming process for a semiconductor region for alpha-ray countermeasure and to prevent soft errors due to the alpha rays, by using a mask for forming a direct contact part, and forming the semiconductor region for alpha-ray countermeasure. CONSTITUTION:A p type well region 2 is formed on the specified main surface part of a semiconductor substrate 1. A field insulating film 3 is formed at the specified parts of the semiconductor substrate 1 and the well region 2. A p-type channel stopper region 4 is formed at the specified part of the well region 2. An insulating film 5 is formed on the semiconductor substrate 1, which serves as a semiconductor-element forming region, and on the upper part of the main surface of the well region 2. A mask 19 for forming contact holes 6 at a direct contact part is formed. The mask 19 is used, to remove the insulating film 5 which is exposed through the mask. After the contact holes 6 at the direct contact part are formed, the mask 19 is removed. Conducting layers 7A-7D are formed on the field insulating film 3 and the insulating film 5. The conducting layers 7A-7D are connected to the main surface of the specified well region 2 through the contact holes 6.

6. 发明专利

JPH07211801A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPH07211801A
公开(公告)日：1995-08-11
申请号：JP29416794
申请日：1994-11-29
申请人： HITACHI LTD
发明人： MEGURO SATOSHI , UCHIBORI KIYOBUMI , SUZUKI NORIO , MOTOYOSHI MAKOTO , KOIKE ATSUYOSHI
IPC分类号： H01L27/11 , H01L21/8244
摘要： PURPOSE:To improve the level of integration, reduce the power consumption of an SRAM, optimize the load element of the memory cell of the SRAM, and prevent the soft error of the SRAM. CONSTITUTION:In an SRAM, gate electrodes 7, 14 of MISFET's Qd1, Qd2 for loads connected with the drain regions 17B of MISFET's Qd1, Qd2 for driving are formed above the MISFET's Qd1, Qd2 for driving memory cells. The channel forming regions 17A, the source regions 17C and the drain regions 17B of the MISFET's Qd1, Qd2 for loads are formed, via gate insulating films 5, 15, above the gate electrodes 7, 14 of the MISFET's Qd1, Qd2 for loads. By the above means, it becomes possible that the flip-flop circuit of the memory cell is turned into a perfect CMOS type and the ratio of the current quantity at the time of operating of the load element to the current quantity at the time of waiting of the load element is increased. Hence the power consumption can be reduced. Since the MISFET's for loads are formed above the MISFET's for driving, the memory cell area is reduced, and the high level integration of an SRAM is realized.

7. 发明专利

JPH0763402A AIR CONDITIONER 失效
公开(公告)号：JPH0763402A
公开(公告)日：1995-03-10
申请号：JP21373693
申请日：1993-08-30
申请人： HITACHI LTD
发明人： OKABE IKUAKI , KISHI SHIGERU , INOUE TORU , ONO SATOSHI , SHONO HIROYUKI , MOTOYOSHI MAKOTO , SUDO KAZUHIRO
IPC分类号： F24F11/02
摘要： PURPOSE:To correspond with an indoor device or an outdoor device for receiving electrical power by a method wherein the indoor device and the outdoor device are provided with a modulating circuit and a demodulating circuit, respectively, and a communication between an indoor control circuit and an outdoor control circuit is carried out by being overlapped with a connection line for supplying a DC power source. CONSTITUTION:Electrical power can be received from both an indoor device 13 and an outdoor device 14 through a changing-over operation of a switch 23. In the case the electrical power is received from the outdoor device, a commercial electrical power 9-a is supplied to a DC power supply circuit 12 and in turn in the case that an electrical power is received from the indoor device, a commercial power source 9-b is received at the indoor device 13 and then the commercial power source 9-b is supplied to the DC power source circuit 12 through a connection line 18. Communication between an indoor control circuit 10 and an outdoor control circuit 11 is carried out such that it is overlapped to a connecting line 19 through a modulating or demodulating circuit 17-a at the indoor device 13 and a modulating or demodulating circuit 17-b at the outdoor device 14 connected to a connection line 19 for supplying the DC power source. With such an arrangement as above, it is possible to receive electrical power from either the indoor device 13 or the outdoor device 14.

8. 发明专利

JPH0382126A MANUFACTURE OF SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPH0382126A
公开(公告)日：1991-04-08
申请号：JP21738289
申请日：1989-08-25
申请人： HITACHI LTD , HITACHI DEVICE ENG
发明人： SUWAUCHI NAOKATSU , SAGAWA MASAKAZU , OTSUKA FUMIO , SHIOTANI KIMIHIRO , KOJIMA MASAYUKI , KIGUCHI YASUO , KOMORI KAZUHIRO , MOTOYOSHI MAKOTO
IPC分类号： H01L21/3205
摘要： PURPOSE:To bury the proper quantity of W films in multiple connecting holes in different depths by a method wherein the first connecting hole to connect a wiring to one side semiconductor region of a MOSFET is provided on a gate electrode while the second connecting hole to connect another wiring to the gate electrode is provided on a field insulating film. CONSTITUTION:A connecting hole 10a to connect a wiring 12a to an n-type semiconductor regions 5b of one side MOSFET is provided on a gate electrode 4 while another connecting hole 10b to connect another wiring 12b to the gate electrode 4 is provided on a field insulating film 2. Accordingly, the depths of the connecting holes 10a, 10b are almost equalized thereby enabling the proper quantity of W films 11 to be buried in the respective connecting holes 10a, 10b. Furthermore, the surface of an interlayer insulating film 9 is flattened not to form any stepped parts between the wirings 12a, 12b formed on the interlayer insulating film 8 so that the depths of the connecting holes 10a, 10b respectively connecting the wirings 12a and 12b to the upper wiring may be naturally equalized with each other thereby enabling the proper quantity of W films 11 to be buried in the respective connecting holes 10a, 10b.

9. 发明专利

JPH02284466A SEMICONDUCTOR STORAGE DEVICE 失效
公开(公告)号：JPH02284466A
公开(公告)日：1990-11-21
申请号：JP10444189
申请日：1989-04-26
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： MOTOYOSHI MAKOTO , SUZUKI NORIO , TAKAHASHI MASATO , MATSUDA NOZOMI
IPC分类号： H01L27/04 , H01L21/822 , H01L21/8244 , H01L27/11
摘要： PURPOSE:To suppress the creation of a soft error without causing a disadvantage such as the degradation of a junction breakdown strength, etc., by a method wherein two storage nodes of a flip-flop circuit which holds information statically are connected to each other through a capacity element having a specific composition. CONSTITUTION:N-type channel driving MIS-FET's Q1 and Q2 are connected to resistors R1 and R2 respectively in series in a memory cell SRAM. The gate electrodes of the MIS-FET's Q1 and Q2 are connected to storage nodes N2 and N1 respectively and the nodes N1 and N2 are connected to data lines DL and DL' through selecting MIS-FET's QS1 and QS2 respectively. Further, the gate electrodes of the MIS-FET's QS1 and QS2 are connected to a word line WL. When information is written, a high potential is applied to the lines WL and DL and a low potential is applied to the line DL' and the node N1 is maintained at a high level and the node N2 is maintained at a low level. Even if alpha-rays penetrate into the memory cell and the node potential is undesirably lowered, as a capacity element Ci always tends to maintain the potential difference between its terminals constant, the inversion of the potentials of the nodes N1 and N2, i.e., a soft error, is hardly created.

10. 发明专利

JPH01144673A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPH01144673A
公开(公告)日：1989-06-06
申请号：JP30546587
申请日：1987-11-30
申请人： HITACHI LTD
发明人： MEGURO SATOSHI , UCHIBORI KIYOBUMI , SUZUKI NORIO , MOTOYOSHI MAKOTO , KOIKE ATSUYOSHI
IPC分类号： H01L21/822 , H01L21/8244 , H01L27/04 , H01L27/11
摘要： PURPOSE:To shield an electric field effect from a gate electrode, and to optimize each of the quantity of currents at the time of operation and the quantity of currents at the time of stand-by of a MISFET for load independently by forming the gate electrode for the MISFET for load to the upper section of a MISFET for drive in a memory cell and shaping the gate electrode so as to cover the inside of the memory cell. CONSTITUTION:A memory cell is formed to the main surface section of a p-type well region 2 shaped to the main surface section of an n type semiconductor substrate 1 composed of single crystal silicon. A depletion layer is formed into a gate electrode (a polycrystalline silicon film) 14 by an electric field effect from a gate electrode 7 for a MISFETQd1 or Qd2 for drive, and the electric field effect from the gate electrode 7 is shielded by the gate electrode 14. A flip-flop circuit for the memory cell is changed into a complete CMOS type by shaping a channel forming region 17A, a source region 17C and a drain region 17B in a MISFETQp for load, the ratio of the quantity of currents at the time of operation to the quantity of currents at the time of stand-by of the FETQp can be increased, and power consumption is lowered. The FETQp is arranged to the upper section of the MISFETQd for drive, thus reducing the area of the memory cell, then improving the degree of integration.

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