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    • 2. 发明专利
    • Electronic component
    • 电子元件
    • JP2005150535A
    • 2005-06-09
    • JP2003388222
    • 2003-11-18
    • Hitachi Cable LtdHitachi Ltd日立電線株式会社株式会社日立製作所
    • OGINO MASAHIKOSATO TOSHIYAHOJO BOUROMOTOWAKI NARIHISAAMO SATORU
    • H05K3/46
    • PROBLEM TO BE SOLVED: To provide an electronic component without the missing or failure of plating wiring by surely forming a power feeding film for electric plating even when wiring patterns are densely arranged with the large number of layers. SOLUTION: This electronic component with the structure of lamination is configured of a substrate 1, wiring layers, insulating layers 9, 12, 15 and 18 and external connecting terminals, wherein the wiring layers and the insulating layers are alternately formed on the substrate 1, and only a portion of the insulating layer terminals 9, 12, 15 and 18 is formed with at least one inclined structure for electric plating power supply. The number of the wiring layers and the insulating layers is piled up, and even when the ends of the insulating layers are shaped so as to be steep, a power supply line can be secured. As a result, even when the number of lamination is increased, the wiring layers can be surely formed, and the electronic component without wiring missing can be provided. COPYRIGHT: (C)2005,JPO&NCIPI
    • 要解决的问题:即使当布线图案以大量层压密布置时,通过确保形成用于电镀的供电膜来提供电子部件而不会出现电镀布线的缺失或故障。 解决方案:具有层叠结构的电子部件由基板1,布线层,绝缘层9,12,15和18以及外部连接端子构成,其中布线层和绝缘层交替地形成在 基板1,并且只有一部分绝缘层端子9,12,15和18形成有用于电镀电源的至少一个倾斜结构。 堆叠布线层和绝缘层的数量,即使当绝缘层的端部成形为陡峭时,也可以确保电源线。 结果,即使当层叠数量增加时,可以可靠地形成布线层,并且可以提供没有布线的电子部件。 版权所有(C)2005,JPO&NCIPI
    • 8. 发明专利
    • Semiconductor device and connection structure, and method for manufacturing the semiconductor device
    • 半导体器件和连接结构以及制造半导体器件的方法
    • JP2011077225A
    • 2011-04-14
    • JP2009225906
    • 2009-09-30
    • Hitachi Ltd株式会社日立製作所
    • KAJIWARA RYOICHIITO KAZUTOSHIMOTOWAKI NARIHISAMATSUYOSHI SATOSHIHIRAMITSU SHINJI
    • H01L21/52B23K35/14B23K35/22
    • H01L24/01H01L2224/8384H01L2924/351H01L2924/00
    • PROBLEM TO BE SOLVED: To provide a low-cost mounting structure excellent in thermal/electrical properties, temperature cycle reliability and high temperature resistance while using a lead-free material having a high melting point since thermal stress in the shearing direction is high wherein the stress is generated in a chip due to a thermal expansion difference, thereby producing a chip crack when a lead-free hard high-temperature solder or high-strength nano Ag is used for joining, and accordingly lead free is not achieved in a semiconductor device required to have a heat resistance of 250°C, in a mounting structure where a semiconductor chip is sandwiched with Cu electrodes. SOLUTION: In a structure of a semiconductor device, a low thermal expansion plate is inserted between a semiconductor chip and each Cu electrode, and each chip side is joined via a high-temperature lead-free solder while each Cu electrode side is joined via a porous Ag layer having a porosity of 20-70%. COPYRIGHT: (C)2011,JPO&INPIT
    • 解决的问题:为了提供一种使用具有高熔点的无铅材料,因为在剪切方向上的热应力是热/电特性,温度循环可靠性和耐高温性优异的低成本安装结构, 高,其中由于热膨胀差而在芯片中产生应力,从而当使用无铅硬质高温焊料或高强度纳米Ag进行接合时产生芯片裂纹,因此无法实现无铅 在半导体芯片夹在Cu电极的安装结构中,要求具有250℃的耐热性的半导体器件。 解决方案:在半导体器件的结构中,在半导体芯片和每个Cu电极之间插入低热膨胀板,并且通过高温无铅焊料将每个芯片侧接合,而每个Cu电极侧为 通过孔隙率为20-70%的多孔Ag层连接。 版权所有(C)2011,JPO&INPIT