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1. 发明专利

JP2000057005A SEMICONDUCTOR PROCESSOR 失效
公开(公告)号：JP2000057005A
公开(公告)日：2000-02-25
申请号：JP14268199
申请日：1999-05-24
申请人： HITACHI LTD , HITACHI ULSI SYS CO LTD
发明人： KUBOTA HIDEO , OIZUMI MASAYASU , KAMIMURA MINORU , SUZUKI JUN , YOSHIDA YOSHINORI , YAMAZAKI TAKANAGA , KURAKAZU KEIICHI
IPC分类号： G06F11/22 , G06F13/28 , G06F15/78
摘要： PROBLEM TO BE SOLVED: To suppress the number of external terminals which are increased by outputting information for identifying a data transfer channel related to a data transfer request by a master chip, to a minimum in the case of providing a direct memory access(DMA) transfer request generated in a slave chip to the master chip. SOLUTION: A microcomputer 1 formed with a central processing unit 100 and a DMA transfer control circuit 102 having plural transfer control channels or the like has a mode terminal 115 for stetting a first or second mode. Each transfer control channel starts data transfer control in response to the DMA transfer request from a DMA transfer request source allocated to the transfer control channel in the first mode of the microcomputer and encodes and outputs the DMA transfer request designating the transfer control channel in place of responding to the DMA transfer request from the DMA transfer request source allocated to the transfer control channel in the second mode of the microcomputer.

2. 发明专利

JPH07134701A SINGLE CHIP MICROCOMPUTER 失效
公开(公告)号：JPH07134701A
公开(公告)日：1995-05-23
申请号：JP3647294
申请日：1994-02-09
申请人： HITACHI LTD , HITACHI MICOM SYST KK
发明人： KAWASAKI SHUNPEI , KURAKAZU KEIICHI , HASEGAWA ATSUSHI , MATSUBARA KIYOSHI , NOGUCHI YOSHIKI , HAYAKAWA AKIO , ITOU YOSHITAKA , AKAO YASUSHI , OSUGA HIROSHI
IPC分类号： G06F13/28 , G06F9/30 , G06F9/302 , G06F9/38 , G06F12/00 , G06F12/08 , G06F13/36 , G06F13/40 , G06F15/78 , H04L12/28
摘要： PURPOSE:To attain high performance, high function and low power consumption. CONSTITUTION:A central processing unit (CPU) and a cache data memory(CDM) are connected to a divided 1st bus B1, a direct memory access control circuit (DMAC) and an outside bus interface (OBIF) are connected to a 2nd bus B2, a brake controller (UBC) having a bus transciever function for selectively connecting 1st and 2nd address buses AB1, AB2 is connected to the 1st and 2nd buses B1, B2, and a peripheral module is connected to a 3rd bus B3 to be a low speed bus cycle lower than 1st and 2nd bus cycles. A bus state controller (BSC) is synchronized with data transfer between the 2nd and 3rd buses B2, B3. Since the load capacity of a signal transmission route is reduced by dividing an internal bus into three parts, signal transmission can be accelerated and power consumption can be reduced by separating the peripheral module not requesting operation speed.

3. 发明专利

JPH05197546A MICROCOMPUTER AND DIVIDING CIRCUIT 失效
公开(公告)号：JPH05197546A
公开(公告)日：1993-08-06
申请号：JP15452592
申请日：1992-05-21
申请人： HITACHI LTD , HITACHI MICOM SYST KK , HITACHI VLSI ENG
发明人： KAWASAKI SHUNPEI , TAWARA YASUHIRO , FUKADA KAORU , YAMAZAKI TAKANAGA , SAKAKIBARA EIJI , KURAKAZU KEIICHI , AKAO YASUSHI , BABA SHIRO , KIHARA TOSHIMASA , KASHIWAGI YUUGO , FUJITA HIDEYA , ISHIDA KATSUHIKO , SAWA NORIKO , ASANO YOICHI , CHAGI HIDEAKI , SUGAWARA MASAHIKO , UMINAGA MASAHIRO , NOGUCHI YOSHIKI , WATABE MITSURU , TSUKAMOTO TAKU , MASUMURA SHIGEKI
IPC分类号： G06F9/28 , G06F7/483 , G06F7/52 , G06F7/527 , G06F7/535 , G06F7/537 , G06F9/30 , G06F9/302 , G06F9/305 , G06F9/318 , G06F9/32 , G06F9/38
摘要： PURPOSE:To decrease program capacity or improve the utilization efficiency of a program memory by employing a fixed length instruction format which is smaller in the number of bits than the maximum length of data words supplied to an instruction executing means. CONSTITUTION:The microcomputer has RISC(reduced instruction set type computer) type architecture and has the fixed length instruction format. When data and instructions are transferred, a bus, e.g. an internal data bus IDB is of 32-bit constitution, but the instructions are in 16-bit fixed length instruction format. Then 16-bit instruction buffers (instruction queue) IRH and IRL store the instructions, one by one, and the instructions are loaded respectively in a single instruction fetch cycle. The instructions are transferred in 32-bit units through the internal data bus IDB and then loaded in an instruction register IR1 through a multiplexer MPX. Then the 16-bit instruction register IR1 holds the instructions present in an instruction decoding stage.

4. 发明专利

JPS6419445A DATA STORAGE SYSTEM 失效
公开(公告)号：JPS6419445A
公开(公告)日：1989-01-23
申请号：JP17470987
申请日：1987-07-15
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG
发明人： TAKANO MAKOTO , HOSHI YASUHIKO , KURAKAZU KEIICHI , BABA SHIRO
IPC分类号： G06F12/08 , G06F12/02 , G06F12/04 , G06F13/00
摘要： PURPOSE:To improve the memory use efficiency and to shorten the data read time by preventing the occurrence of an ineffective buffer area which is left unused and only taking one descriptor to obtain the leading address of a buffer area where desired data is stored. CONSTITUTION:A leading address TA of the buffer area where reception data of one frame is stored is described in a first pointer PNT1 of a descriptor DD1, and a leading address DTA of the memory area where a descriptor DD2 following the descriptor DD1 is stored is described in a second pointer PNT2. Each descriptor DD is provided with an indication column DES where a data delimiter signal indicating whether reception data is terminated in the indicated buffer area or not is described. Since the number of buffer areas used for each frame is changed in accordance with the length of data of a variable length frame, the ineffective buffer area is reduced and only one descriptor is taken to immediately obtain the leading address of data of the next frame. Thus, the buffer memory use efficiency is improved and the data read time is shortened.

5. 发明专利

JPS63263535A DATA PROCESSING SYSTEM 失效
公开(公告)号：JPS63263535A
公开(公告)日：1988-10-31
申请号：JP9734587
申请日：1987-04-22
申请人： HITACHI LTD
发明人： KURAKAZU KEIICHI , OTA YUJI , KIDA HIROYUKI
IPC分类号： G06F9/34
摘要： PURPOSE:To eliminate need of addition of new instruction for access to special registers in case of the increase of the number of special registers by providing an operation code designating field including common information and a position designating field. CONSTITUTION:The instruction which accesses a special register is set to the format where an operation code designating field OP, which is given in accordance with contents of the instruction and designates the same operation code independently of the classification of the register, and a register designating field CR indicating information concerning the special register such as the register number assigned to the special register and the register size are provided independently of each other. Thus, a desired special register is accessed by not changing the operation code but only changing the register number or the like, and addition of new operation codes for access to special registers is unnecessary in case of the increase of the number of special registers.

6. 发明专利

JPS63163638A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPS63163638A
公开(公告)日：1988-07-07
申请号：JP30843786
申请日：1986-12-26
申请人： HITACHI LTD
发明人： KURAKAZU KEIICHI , MARUYAMA TAKASHI
IPC分类号： G06F9/48 , G06F13/24 , G06F15/78
摘要： PURPOSE:To improve integrating density and universal applicability, by providing a microprocessor incorporating an interruption control circuit which generates a vector corresponding to an interruption request from an interruption signal and an offset signal. CONSTITUTION:An interruptive operation is performed by providing local interruption control circuits INC (0-n) which send the interruption signal to a CPU corresponding to one or plural kinds of interruption factors supplied from peripheral circuits I/O (0-n) and receive interruption acknowledge signals ACK (0-n) transferred from the CPU, and also, output the offset signal corresponding to the interruption factor, responding them in one to one, and providing the interruption control circuit INC which generates a vector address corresponding to the interruption request from the interruption signals and the interruption request, in the CPU. Since only the offset signal consisting a few number of signals is sent out from the local interruption control circuit INC (0-n), it is possible to reduce the number of signal lines, and also, it is possible to realize standardization because the vector goes to a relative vector consisting of the interruption control signal and the offset signal.

7. 发明专利

JPS6354630A DATA PROCESSOR 失效
公开(公告)号：JPS6354630A
公开(公告)日：1988-03-09
申请号：JP19714686
申请日：1986-08-25
申请人： HITACHI LTD
发明人： SUGAI MASARU , KURAKAZU KEIICHI , KIDA HIROYUKI
IPC分类号： G06F9/46 , G06F7/00 , G06F7/57 , G06F9/22 , G06F9/48
摘要： PURPOSE:To prevent arithmetic operation speed from decreasing in an execution unit, even when a general register is provided out-side the execution unit, by inputting a data supplied from the general register through a buffer register coupled directly to an arithmetic operation logic unit, to the arithmetic operation logic unit. CONSTITUTION:For instance, a general register group 8 consisting of plural register sets in which 16 pieces of registers form one set is provided outside the execution unit 6. A data in this general register group 8 can be supplied to a buffer register 9 coupled directly only to one input terminal of an arithmetic operation logic unit ALU, through a multiplexer MPX. Also, to the other input terminal of the arithmetic operation logic unit ALU, a read bus RB in the execution unit 6 is connected. That is to say, according to such a constitution, only the buffer register 9 is connected to one input terminal of the arithmetic operation logic unit ALU, and the read bus RB in the execution unit 6 is constituted of only one piece. In such a way, the speed for calculating an effective address, etc., is increased.

8. 发明专利

JPS6352240A DATA PROCESSOR 失效
公开(公告)号：JPS6352240A
公开(公告)日：1988-03-05
申请号：JP19530186
申请日：1986-08-22
申请人： HITACHI LTD
发明人： KURAKAZU KEIICHI
IPC分类号： G06F9/46 , G06F9/48
摘要： PURPOSE:To process data at high speed via a context switching action or return by switching designation of register groups in response to a context switch and at the same time performing the saving control of contents so that at least one register group is always set in an idle state. CONSTITUTION:The using states of three register groups A-C are shown by a condition register CR. When a context switching action is carried out in application modes of both register groups A and B and in a non-application mode of the register group C, this group C is immediately used for execution of a program. In this case, the contents of the group B are held as they are and a direct memory access control circuit DMAC is started since all groups A-C are used. Thus the contents of the group A are saved to an external memory. These saved contents are sent back to the group A when the group C becomes idle.

9. 发明专利

JPS613222A DATA PROCESSOR 失效
公开(公告)号：JPS613222A
公开(公告)日：1986-01-09
申请号：JP12177184
申请日：1984-06-15
申请人： HITACHI LTD
发明人： KURAKAZU KEIICHI
IPC分类号： G06F1/14 , G06F1/04 , G06F15/78
摘要： PURPOSE:To reduce the occupation area of a timer circuit by providing the >=2 2nd buses connected to the internal bus of a microcomputer, and connecting a constant register, etc., to one bus and a counter register, etc., to the other. CONSTITUTION:A single-chip microcomputer MPU consists of a CPU1, ROM2, RAM3, timer circuit 5, input/output port 6, etc., which are connected mutually through the internal bus 7. For this purpose, a time-sharing (TSS) bus 8 is provided as the 2nd bus in the timer circuit 5 and connected to said internal bus 7 through a switching circuit 9 which is controlled with the signal from a control part 10. This TSS bus 8 consists of three buses 8a-8c and forms two sequences of buses; the counter register CNT-REG and constant register CST-REG are connected through gates Ga-Gc respectively and a common counter CNT and a comparator CMP are also connected, so that substantially three timers are put in operation simultaneously.

10. 发明专利

JPS60211561A Microcomputer 失效
标题翻译： MICROCOMPUTER
公开(公告)号：JPS60211561A
公开(公告)日：1985-10-23
申请号：JP6769084
申请日：1984-04-06
申请人： Hitachi Ltd
发明人： KURAKAZU KEIICHI , KEIDA HARUO
IPC分类号： G06F11/22 , G06F15/78
摘要： PURPOSE: To attain data transmission/reception between an incorporated RAM and an external device in high speed by providing a function separating the microprocessor and an internal bus to decrease the testing time.
CONSTITUTION: In testing a RAM or a ROM, a level of a control signal BC is made to a high level ahead the conduction of the test so as to separate the microprocessor CPU and the internal bus BUS. Then an address signal is applied from an external terminal to select directly the RAM or the ROM. In case of the ROM, the content is read and extracted externally via an I/O, compared with a prescribed expected value and its propriety is discriminated. In case of the RAM, the content is read similarly, and its propriety is discriminated by comparing it with the written data. The testing time is decreased by testing the device directly from the external terminals in this way and the data is transmitted/received with an external device in high speed.
COPYRIGHT: (C)1985,JPO&Japio
摘要翻译：目的：通过提供分离微处理器和内部总线的功能来降低测试时间，实现高速内置RAM和外部设备之间的数据传输/接收。规定：在测试RAM或ROM时，在测试的导通之前将控制信号BC的电平提高到高电平，以分离微处理器CPU和内部总线BUS。然后从外部端子施加地址信号，直接选择RAM或ROM。在ROM的情况下，与规定的预期值相比，通过I / O从外部读取和提取内容，并且鉴别其适当性。在RAM的情况下，类似地读取内容，并且通过将其与写入的数据进行比较来区分其适当性。通过以这种方式直接从外部终端测试设备，并且用外部设备高速发送/接收数据，可以减少测试时间。

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