专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明专利

JPH07134701A SINGLE CHIP MICROCOMPUTER 失效
公开(公告)号：JPH07134701A
公开(公告)日：1995-05-23
申请号：JP3647294
申请日：1994-02-09
申请人： HITACHI LTD , HITACHI MICOM SYST KK
发明人： KAWASAKI SHUNPEI , KURAKAZU KEIICHI , HASEGAWA ATSUSHI , MATSUBARA KIYOSHI , NOGUCHI YOSHIKI , HAYAKAWA AKIO , ITOU YOSHITAKA , AKAO YASUSHI , OSUGA HIROSHI
IPC分类号： G06F13/28 , G06F9/30 , G06F9/302 , G06F9/38 , G06F12/00 , G06F12/08 , G06F13/36 , G06F13/40 , G06F15/78 , H04L12/28
摘要： PURPOSE:To attain high performance, high function and low power consumption. CONSTITUTION:A central processing unit (CPU) and a cache data memory(CDM) are connected to a divided 1st bus B1, a direct memory access control circuit (DMAC) and an outside bus interface (OBIF) are connected to a 2nd bus B2, a brake controller (UBC) having a bus transciever function for selectively connecting 1st and 2nd address buses AB1, AB2 is connected to the 1st and 2nd buses B1, B2, and a peripheral module is connected to a 3rd bus B3 to be a low speed bus cycle lower than 1st and 2nd bus cycles. A bus state controller (BSC) is synchronized with data transfer between the 2nd and 3rd buses B2, B3. Since the load capacity of a signal transmission route is reduced by dividing an internal bus into three parts, signal transmission can be accelerated and power consumption can be reduced by separating the peripheral module not requesting operation speed.

2. 发明专利

JPH06162225A SINGLE CHIP MICROCOMPUTER INCORPORATED WITH SELF-TEST FUNCTION 失效
公开(公告)号：JPH06162225A
公开(公告)日：1994-06-10
申请号：JP30674792
申请日：1992-11-17
申请人： HITACHI LTD
发明人： OSUGA HIROSHI , NOGUCHI YOSHIKI , KATO KANJI
IPC分类号： G06F11/22 , G06F13/00 , G06F15/78
摘要： PURPOSE:To automatically detect a fault of a built-in peripheral module by retaining a result obtained at the time when it is assumed that there is no fault at the time of test operation of the inside of the peripheral module, and comparing this expected value with the result of operation. CONSTITUTION:To a peripheral module 102, a test operation setting means 205, an expected value retaining means 206 and a comparing means 207 are added, and the expected value retaining means 206 retains a result obtained at the time when it is assumed that there is no fault at the time of test operation. In such a state, when the peripheral module 102 is in a test operation state, the test operation setting means 205 fetches a test operation set value sent from a CPU 100, a control means 201 generates a control signal of a data bus 200 based on this set value, and the data bus outputs the result of execution of a test. The comparing means 207 compares this result of execution and an expected value outputted from the expected value retaining means 206, and outputs a fault detecting signal to an interruption control circuit 103, in the case of noncoincidence. Accordingly, the fault of the peripheral module can be detected in the course of operation of a microcomputer.

3. 发明专利

JPH05249194A 失效
公开(公告)号：JPH05249194A
公开(公告)日：1993-09-28
申请号：JP4823792
申请日：1992-03-05
申请人： HITACHI LTD
发明人： OSUGA HIROSHI , NOGUCHI YOSHIKI
IPC分类号： G01R31/28 , G06F11/22
摘要： PURPOSE:To reduce the number of executing steps at the time of writing the same value in a plurality of registers and to reduce the number of testing steps at the time of testing the registers by incorporating a signal line for controlling write signals from the outside and a little amount of hardware in the title logic LSI. CONSTITUTION:A high-level signal having one cycle length is sent to a register latch-write signal 20 from an instruction decoder 102a synchronously to the rise of a PHI2-signal line 204 in a state where a switch signal line 205 is at a low level. Since the outputs of OR gates 150, 151, and 152 become high levels and the output of an AND gate 140 becomes a low level, no collision occurs between writing and reading. The outputs of AND gates 130, 132, and 134 in a register block circuit 101 become high levels synchronously to the rise of a PHI1-signal line 203. Therefore, the data inputted from an external input 200 are simultaneously written in registers 110 and ill at the timing of the signal line 203. As a result, the number of executing steps can be reduced.

4. 发明专利

JPH03263162A DATA PROCESSOR 失效
公开(公告)号：JPH03263162A
公开(公告)日：1991-11-22
申请号：JP6102790
申请日：1990-03-14
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG
发明人： OSUGA HIROSHI , SAWASE TERUMI , AKAO YASUSHI , KONO TATSUHIKO
IPC分类号： G06F15/16
摘要： PURPOSE:To improve the processing capacity of the whole system by executing a data transfer to a timer by a sub-processor operated as DMAC by the micro- instruction control, and also, reforming the micro-instruction control. CONSTITUTION:The micro-instruction control is executed so that a second processor (sub-processor) 131 executes a DMAC (Direct Memory Access) function. The sub-processor 131 receives a data transfer request signal from a data processor 114, and transfers data on a data memory 137 to a timer 130 without allowing it to pass through a first processor (CPU) 112. Also, the micro- instruction control is reformed so that the sub-processor 131 can execute an arithmetic processing of data to be sent to the data processor 114, executed by the CPU 112. In such a way, the data transfer is executed at a high speed, and the system performance can be improved.

5. 发明专利

JPH0566965A BREAK SIGNAL GENERATING MEANS, EVALUATING LOGICAL LSI, AND REGISTER AND MASK BIT OF LSI 失效
公开(公告)号：JPH0566965A
公开(公告)日：1993-03-19
申请号：JP22688391
申请日：1991-09-06
申请人： HITACHI LTD
发明人： OSUGA HIROSHI , FUKADA KAORU
IPC分类号： G06F11/22 , G06F11/28 , G06F15/78
摘要： PURPOSE:To increase the response speed of a break signal together with prevention of the increase of area of a logical LSI for mass production by building a break signal generating circuit that is so far built in an ICE (i-circuit emulator) into an evaluating logical LSI-only logical part of an evaluating logical LSI. CONSTITUTION:The desired conditions to be broken are previously set to a break point setting register 104 through an ICE data bus 202. When a logical LSI 102 for mass production is actuated, the value is outputted to an address bus 201. This value is compared with the break conditions by a comparator 107. Then a break signal is outputted through a break signal line 200 when the coincidence is obtained between the output value and the break conditions. Then the response speed of the break signal is increased owing to a short distance set between the LSI 102 and a break signal generating signal.

6. 发明专利

JPH0784963A SEMICONDUCTOR INTEGRATED CIRCUIT WITH CPU 失效
公开(公告)号：JPH0784963A
公开(公告)日：1995-03-31
申请号：JP23123393
申请日：1993-09-17
申请人： HITACHI LTD
发明人： OSUGA HIROSHI , NOGUCHI YOSHIKI , UCHIYAMA KUNIO , NENE YOSHITO , IKEDA HIROSHI , AMANO AKIO , KAMIMAKI HARUO , ASAKAWA YOSHIAKI
IPC分类号： G06F13/14 , G06F15/16
摘要： PURPOSE:To improve the efficiency of the data arithmetic processing of multiple CPUs by performing an interruption request processing from a peripheral module at a high speed. CONSTITUTION:Peripheral modules 11, 12, and 13 are connected to an I/O system data bus 201, an interruption control circuit 17 is connected to an I/O system processor 101 and the peripheral modules, and an interruption control circuit 17 transfers interruption requests from the peripheral modules to the I/O system processor 101. The peripheral modules need to perform data transfer through an I/O system data bus 102 and selecting circuits 18 and 19 when sending or receiving data to or from outside the chip. The data transfer between the peripheral modules and the outside of the chip through the I/O system data bus 102 is performed under the control of the I/O system processor 101, so an interruption request for this data transfer is not sent to an arithmetic system processor 100.

7. 发明专利

JPH03288939A CLOCK CONTROL CIRCUIT 失效
公开(公告)号：JPH03288939A
公开(公告)日：1991-12-19
申请号：JP9030390
申请日：1990-04-06
申请人： HITACHI LTD
发明人： OSUGA HIROSHI , IWASAKI KAZUHIKO , YAMAGUCHI NOBORU , AKAO YASUSHI , TSUCHIYA FUMIO
IPC分类号： G01R31/28 , G06F1/04 , G06F11/22 , G06F13/00
摘要： PURPOSE:To detect the fault, which can not be detected normally, of a bus transfer circuit by providing a clock control circuit to directly control a clock in the partial circuit of a logic circuit. CONSTITUTION:A control circuit 100, bus circuit 101 and clock control circuit 102 are provided. This added clock control circuit 102 is composed of OR gates 118 and 119 and inverter 120. In such a case, by controlling two-phase clocks phi1 and phi2 in the partial circuit of the logic circuit, the clocks phi1 and #2 supplied by the partial circuit of the logic circuit are fixed to a high level or a low level. Thus, since the clock in the partial circuit of the logic circuit can be controlled, it is possible to detect the fault, which can not be detected normally, of the bus transfer circuit.

8. 发明专利

JP2003131873A MICROCOMPUTER 审中-公开
公开(公告)号：JP2003131873A
公开(公告)日：2003-05-09
申请号：JP2002259483
申请日：2002-09-05
申请人： HITACHI LTD
发明人： OSUGA HIROSHI , KIUCHI ATSUSHI , HASEGAWA HIRONORI , UMAJI TORU , NOGUCHI YOSHIKI , AKAO YASUSHI , BABA SHIRO
IPC分类号： G06F9/38 , G06F9/30 , G06F9/318 , G06F9/32 , G06F15/78
摘要： PROBLEM TO BE SOLVED: To suppress growth in logic size such as an instruction decode circuit in a microcomputer in which a DSP engine is mounted on a single LSI together with a CPU core. SOLUTION: This microcomputer is constituted with a CPU (2), a memory unit which access is trolled by the CPU, a data bus to transfer between the above memory unit and the above CPU, and a DSP (3) connected to the above data bus. The CPU has a CPU instruction of 16 bit fixed length, an instruction register (25) to fetch a DSP instruction of 16 bit or 32 bit length for the DSP, and a decoder (24) to generate the first control signal (247) to identify the CPU instruction or the DSP instruction based on a part of the instruction fetched by the above instruction register and control behavior of the CPU in accordance with an outcome of identification, and the second control signal (20) to control the behavior of the DSP. The DSP includes a decoder (34) to decode the second control signal received from the CPU.

9. 发明专利

JPH0922379A MICROCOMPUTER 失效
公开(公告)号：JPH0922379A
公开(公告)日：1997-01-21
申请号：JP34744195
申请日：1995-12-14
申请人： HITACHI LTD
发明人： OSUGA HIROSHI , KIUCHI ATSUSHI , HASEGAWA HIRONORI , UMAJI TORU , NOGUCHI YOSHIKI , AKAO YASUSHI , BABA SHIRO
IPC分类号： G06F12/06 , G06F9/30 , G06F9/34 , G06F9/38 , G06F13/16 , G06F15/78
摘要： PROBLEM TO BE SOLVED: To accelerate a digital signal processing in a microcomputer for which a DSP engine is mounted on one LSI along with a CPU core. SOLUTION: A built-in memory is turned to the two surfaces of first memories 5, 7 and second memories 4, 6 and they are respectively made parallelly accessible by third buses XAB, XDB and second buses YAB, YDB. Thus, the CPU core 2 can simultaneously transfer the two pieces of data from the built-in memory to the DSP engine 3. Also, the third buses XAB, XDB and the second buses YAB, YDB are distinguished from first buses IAB, IDB to be external interfaces and the CPU core 2 can access an external memory parallelly to the access of the second memories 4, 6 and the first memories 5, 7.

10. 发明专利

JPH0836532A TERMINAL DEVICE OF LOW POWER CONSUMPTION 失效
公开(公告)号：JPH0836532A
公开(公告)日：1996-02-06
申请号：JP16941794
申请日：1994-07-21
申请人： HITACHI LTD
发明人： HANAWA MAKOTO , OSUGA HIROSHI , NOGUCHI YOSHIKI , KANEKO YOSHIYUKI
IPC分类号： G06F1/32 , G06F1/26 , G06F12/16 , G06F15/02
摘要： PURPOSE:To surely save various system data specified by a CPU or data in a RAM through a simple circuit constitution by turning off the power source after transferring specific data to an electrically readable and writable nonvolatile storage means. CONSTITUTION:When a command signal for turning off the power source of the portable terminal device of a low power consumption is inputted, an interruption is generated in the portable terminal device of a low power consumption to save all the contents of a RAM 105 in a flash EPROM 102 as the nonvolatile storage means, and then power line to the CPU 101, the flash EPROM 102, an input/output means 103, the RAM 105, a transfer means 106, and an actuation means 107 is turned off. Namely, the power line to the modules is disconnected after it is confirmed by providing an actuation stop bit 109 that the contents on the RAM 105 are transferred to the flash EPROM 102 when the power source of the portable terminal device of a low power consumption is turned off.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式