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    • 2. 发明专利
    • OVERCURRENT LIMIT CIRCUIT FOR POWER TRANSISTOR
    • JPH08265121A
    • 1996-10-11
    • JP6326595
    • 1995-03-23
    • FUJI ELECTRIC CO LTD
    • MIYASAKA TADASHI
    • H03K17/78H02M7/537H03K17/08H03K17/567
    • PURPOSE: To decrease the number of photocouplers required to deliver a control command between a bridge arm and a command circuit via an insulation path when the power transistor(TR) of a bridge circuit is protected against an overcurrent. CONSTITUTION: An overcurrent limit by a current limit circuit 20 with respect to a power TR of, e.g. an arm 12 in one of an arm 11 toward a power supply potential point V and the arm 12 toward a reference potential point E in a bridge circuit 10 is set lower than an overcurrent limit by the current limit circuit 20 with respect to a power TR of the other arm 12. A command circuit 50 providing control commands Ls, Ss to each power TR 1 in the bridge circuit 10 is operated by the same reference potential E as that for the power TR 1 in the arm 12 whose overcurrent limit is selected lower. The control command Ls is delivered to a drive circuit 30 of the arm 11 via a photocoupler in a form of an optical signal and the control command Ss is delivered to the drive circuit 30 of the arm 12 via a photocoupler in a form of an electric signal.
    • 6. 发明专利
    • POWER TRANSISTOR
    • JPS63275175A
    • 1988-11-11
    • JP11130587
    • 1987-05-07
    • FUJI ELECTRIC CO LTD
    • MIYASAKA TADASHI
    • H01L29/73H01L21/331H01L29/72H01L29/732
    • PURPOSE:To render the balance of an emitter current more adequate so as to improve the breakdown strength and also decrease the loss and the heat induced by a current balance resistive section by a method wherein a gap is provided between a base wiring and a base electrode adjacent to the wire connecting a connecting section of a base wiring connected with a base terminal to a connecting section of an emitter wiring connected with an emitter terminal. CONSTITUTION:A cut section 5 is provided at the base of a base electrode 11 the most adjacent to a wire connecting a bonding section 3 of a base wiring with a bonding section 4 of an emitter wiring. Therefore, a base current 7 flows through a base section 8 of a silicon substrate 10 and is restricted by a base sheet resistor 9 connected with a base in series, so that the convergence of the base current into an emitter electrode positioned at the central part of the substrate is alleviated. Thereby, the balance of a current is rendered adequate and as a base current is smaller than an emitter current, the loss and the heat are made smaller as compared with those induced by the resistor through which a restricted emitter current flows and an additional process is rendered unnecessary, and thus a breakdown strength is improved.
    • 7. 发明专利
    • POWER SEMICONDUCTOR MODULE
    • JP2002203942A
    • 2002-07-19
    • JP2000402127
    • 2000-12-28
    • FUJI ELECTRIC CO LTD
    • KOBAYASHI TAKATOSHIMIYASAKA TADASHIYAMADA KATSUMIMOROZUMI AKIRA
    • H01L23/12H01L23/373H01L25/07H01L25/18H02M7/00
    • PROBLEM TO BE SOLVED: To optimize a ceramic substrate, the quality of material in a metal base, dimensions, a junction material, and a boding method for improving reliability and for lengthening a life in a power semiconductor module. SOLUTION: In this power semiconductor module, a package integrated with terminal is combined with the circuit assembly body of the metal base 1, ceramic substrate 2 and power semiconductor chip 9. In this case, in the ceramic substrate, a front circuit plate 8b and a back plate 8c are joined to both the surfaces of a ceramic plate 8a, and the metal base is soldered to the ceramic substrate. Also, the metal base is made of copper and a copper alloy having a thermal conductivity of 250 W/mK or more, and the plate thickness is set to 3.9 to 6 mm. In the ceramic substrate, the thickness of the ceramic plate is set to 0.1 to 0.65 mm, the thicknesses of the front circuit and back plates are set to 0.1 to 0.5 mm, the external dimensions are set to 50 mm×50 mm maximum, aspect ratio is prescribed from 1:1 to 1:1.2, solder having a melt point of 183 to 250 deg.C is used, and the layer thickness is set to 0.1 to 0.3 mm for bonding the metal base to the ceramic substrate by solder.