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1. 发明专利

JPH07147418A DIODE 失效
公开(公告)号：JPH07147418A
公开(公告)日：1995-06-06
申请号：JP29373093
申请日：1993-11-25
申请人： FUJI ELECTRIC CO LTD
发明人： NISHIURA AKIRA
IPC分类号： H01L29/861
摘要： PURPOSE:To reduce reverse leakage current when a high-speed diode which allows a short reverse recovery time for off-operation and is provided with soft recovery characteristics is turned off. CONSTITUTION:An insulating film 20 is formed on the surface of an n-type semiconductor area 12, a plurality of windows 21 are opened and p-type diode layers 30 are diffused at positions corresponding to the windows 21 on the surface of the semiconductor area 12. An anode terminal surface electrode film 41 is connected only to a diode layer 30 so as to provide insulation from the surface of the semiconductor area 12 by the insulating film 20. Thus, while keeping the excellent soft recovery characteristic which allows no voltage vibration in a short reverse recovery time Tr of the off-operation voltage V and the current I as shown in the figure (b), off-operation current leakage is limited only to the pn junction part between the semiconductor area 12 and the diode layer 30, and the reverse leakage current Ir shown in the figure (d) is remarkably reduced as the characteristic (a) compared with the conventional characteristic (b).

2. 发明专利

JPH06125256A CONTROLLER FOR DOUBLE-GATE TYPE SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH06125256A
公开(公告)日：1994-05-06
申请号：JP8102593
申请日：1993-04-08
申请人： FUJI ELECTRIC CO LTD
发明人： TERASAWA NORIYASU , MIYASAKA TADASHI , NISHIURA AKIRA , NISHIURA SHINJI , SAKURAI KENYA , OTSUKI MASATO
IPC分类号： H01L29/78 , H01L21/336 , H01L27/04 , H03K17/08 , H03K17/56 , H03K17/687 , H01L29/784
摘要： PURPOSE:To provide a controller capable of surely controlling a double-gate type semiconductor device provided with various kinds of superior characteristics such as low switching loss even it is applied to a high frequency by one control signal similarly to a conventional IGBT, etc. CONSTITUTION:The controller 20 comprises a first gate control circuit 21 which supplies the control signal inputted from an input terminal P1 to a gate G1, and a second gate control circuit 22 which supplies the control signal inputted from the input terminal P1 to a gate G2. A delay circuit 31 is installed at the first gate control circuit 21, and an off-signal is supplied to the gate G2, and it is supplied to the gate G1 after a condition is transferred from a thyristor state to a transistor state, which surely stops the double-gate type semiconductor device.

3. 发明专利

JPH04113678A INSULATED GATE BIPOLAR TRANSISTOR 失效
公开(公告)号：JPH04113678A
公开(公告)日：1992-04-15
申请号：JP23302790
申请日：1990-09-03
申请人： FUJI ELECTRIC CO LTD
发明人： NISHIURA AKIRA
IPC分类号： H01L29/68 , H01L29/739 , H01L29/78
摘要： PURPOSE:To eliminate an increase in contact resistance of a fourth region with an emitter electrode by selectively forming a first conductivity type fifth region having a depth deeper than a fourth region and higher impurity concentration than that of a third region on a part including no channel of the surface of the third region, and forming the fifth region of periodically arranged relatively high and low impurity concentration regions. CONSTITUTION:Polycrystalline silicon is deposited on an n type layer 22 through an insulating film 6, a gate electrode is then patterned, and a p-type layer 3 is formed by ion implanting and heat treating with the electrode as a mask. An n type layer is formed by ion implanting arsenic by using the electrode mask and resist mask, and a p-type layer 12 and an n type layer 11 on the part of the layer 12 are formed by ion implanting boron and heat treating by using the resist mask.

4. 发明专利

JPH10321835A MANUFACTURE OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH10321835A
公开(公告)日：1998-12-04
申请号：JP6566698
申请日：1998-03-16
申请人： FUJI ELECTRIC CO LTD
发明人： NISHIURA AKIRA , OTSUKI MASATO
IPC分类号： H01L29/74 , H01L21/332 , H01L29/739 , H01L29/749 , H01L29/78 , H03K17/567
摘要： PROBLEM TO BE SOLVED: To provide a manufacturing method for thyristor semiconductor devices whose hole-extracting second MOSFET has a conductivity type opposite to that of an electron-injection first MOSFET. SOLUTION: After an n type second semiconductor region 3 is grown epitaxially through an n -type buffer layer formed on a P -type semiconductor substrate. On it at positions isolated via the medium of a gate oxide films 9, gate electrodes 10 for first MOSFETs of polycrystalline silicon are formed, and at intermediate sites between them gate electrodes 21 for second MOSFETs are formed. Boron ion implantation is performed with the gate electrodes used as masks. Next, the openings between the external gate electrodes 10 and the internal gate electrodes 21 are coated with resists 42. After that, ion implantation of arsenic, etc., is performed via the openings between the gate electrodes 21, using the gate electrodes and the resists as masks. Next, the resists 42 are removed, and then two kinds of impurities are thermally diffused by being driven-in simultaneously, and deep p-type third semiconductor regions 4 are formed, and shallow n-type fourth semiconductor regions 15 are formed within them.

5. 发明专利

JPH06310726A PROTECTIVE DIODE FOR TRANSISTOR 失效
公开(公告)号：JPH06310726A
公开(公告)日：1994-11-04
申请号：JP9470693
申请日：1993-04-22
申请人： FUJI ELECTRIC CO LTD
发明人： SAITO TATSU , OTSUKI MASATO , NISHIURA AKIRA
IPC分类号： H01L29/772 , H01L27/02 , H01L27/04 , H01L27/06 , H01L29/739 , H01L29/76 , H01L29/78 , H01L29/866 , H01L29/784
摘要： PURPOSE:To limit the diffusion depth of impurities when a diode layer is built in so that an overvoltage protective diode, e.g. an insulated gate transistor, can be fabricated easily within the same chip as the transistor. CONSTITUTION:A p-type diode layer 32 is diffused, while being split into a plurality of sublayers, through a window made in a dielectric film 31 covering the surface of an n-type semiconductor region 2 where a depletion layer extends under OFF state of a transistor 10 to be protected, i.e., a vertical FET. A diode terminal A is led out from an electrode film 34 touching the diode layer 32 conductively to provide a protective diode 30. This structure retards connection of the depletion layers extending from each diode layer 32 into the semiconductor region 2 due to overvoltage and allows lowering of the breakdown voltage of the protective diode 30 sufficiently below the breakdown voltage of the transistor 10 to be protected even if the diffusion depth of the diode layer 32 is shallower by one order than a conventional one.

6. 发明专利

JPH06204410A PROTECTION CIRCUIT FOR INSULATED-GATE CONTROL TRANSISTOR 失效
公开(公告)号：JPH06204410A
公开(公告)日：1994-07-22
申请号：JP143493
申请日：1993-01-08
申请人： FUJI ELECTRIC CO LTD
发明人： NISHIURA AKIRA
IPC分类号： H01L27/06 , H01L29/78 , H03K17/08 , H01L29/784
摘要： PURPOSE:To reduce a current capacitance required by a diode which protects insulated-gate control transistors, including insulated-gate bipolar transistors and field effect transistors, from an overvoltage by a dynamic clamping method, and to reduce the size of the diode. CONSTITUTION:A protective diode 30 having an avalanche breakdown voltage which is lower than a withstand voltage of an insulated-gate control transistor 10 is connected between a gate and a main terminal of the transistor 10. For example, a depletion type bipolar transistor 41 is connected, as a nonlinear element 40 which has a current saturation characteristic, between the gate and a drive circuit 20. When a voltage Vc applied to the transistor 10 exceeds the withstand voltage of the transistor 10, the diode 30 causes breakdown. An avalanche current Id, which flows into the diode 30 while the transistor 10 is temporarily turned on and an overvoltage is absorbed, is limited to a saturation current value of the non-linear element 40 by means of the non-linear element 40, so that the avalanche current is reduced to some fraction of one when compared with an avalanche current fl-owing through a conventional protection circuit.

7. 发明专利

JPH05160121A PLANAR-TYPE SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH05160121A
公开(公告)日：1993-06-25
申请号：JP32487391
申请日：1991-12-10
申请人： FUJI ELECTRIC CO LTD
发明人： NISHIURA AKIRA
IPC分类号： H01L21/318 , H01L21/331 , H01L29/06 , H01L29/73 , H01L29/78
摘要： PURPOSE:To prevent the occurance of a minute crack on the surface of a staged part of a second layer where a minute crack likely happens by forming a protective film which has an excellent mechanical strength on the surface of the staged part of the second layer of relatively low specific resistance which is formed for the purpose of preventing the accumulation of electric charges on an interface between a semiconductor substrate and a surface protective film. CONSTITUTION:In order to protect a part of a p-n junction 6 between an n-type layer 1 and a p-type region 2 of a device which is exposed to the surface, a silicon oxide film 7 of specific resistance 10 -100 OMEGAcm and an a-Si film 8 of specific resistance 10 -10 OMEGAcm are deposited in this order from the substrate, each in the thickness of 1mum. Since the a-Si film 8 has a low specific resistance, it works as a field plate for extending a depletion layer uniformly toward a stopper electrode being at the same potential as a drain electrode when a reverse voltage is applied to the p-n junction 6. This surface protective film has a staged part above an end of the electrode. A nitrode film 9 of 1mum thickness is formed to prevent the occurance of a crack in the staged part of the a-Si film 8. By this method, a planar-type semiconductor device of excellent long-term reliability can be obtained.

8. 发明专利

JPH03290968A MANUFACTURE OF INSULATED GATE BIPOLAR TRANSISTOR 失效
公开(公告)号：JPH03290968A
公开(公告)日：1991-12-20
申请号：JP9171290
申请日：1990-04-06
申请人： FUJI ELECTRIC CO LTD
发明人： NISHIURA AKIRA
IPC分类号： H01L29/78 , H01L21/336 , H01L29/739
摘要： PURPOSE:To make it possible to form fourth and fifth regions in a self-aligning manner without enlarging a channel length even when the deep fourth region is formed, by using a strip-shaped region of polycrystalline silicon as a mask for forming a third region. CONSTITUTION:A polycrystalline silicon layer is deposited on the surface of an n layer 22 (second region) with an insulating film 6 interlaid and patterning is conducted by a technique of photoetching. At this time, strip-shaped polycrystalline silicon layers 10 are formed simultaneously at prescribed intervals from 8 gate electrodes 7. Subsequently, a resist layer 14 is formed so that it fills up a space between the electrode 7 and the layer 10. In succession, boron ions 11 are implanted. Thereafter a p layer (third region) 3 is formed by activating and diffusing implanted boron 15 by heat treatment, and after the layer 14 is removed, a resist layer 16 is provided. The layers 10 and the layer 16 are removed, a resist layer 12 is formed, and then an n layer (fourth region) 4 is formed by heat treatment. By this method, a channel length being usually 5 to 10mum is made to be 5mum or below, and thus it is possible to prevent latch-up substantially and to make an ON-resistance small.

9. 发明专利

JPH0316257A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH0316257A
公开(公告)日：1991-01-24
申请号：JP15096189
申请日：1989-06-14
申请人： FUJI ELECTRIC CO LTD
发明人： NISHIURA AKIRA
IPC分类号： H01L29/68 , H01L21/8249 , H01L27/04 , H01L27/06 , H01L29/78
摘要： PURPOSE:To smoothen the fluctuation of an ON-voltage at the time of turning-ON with a very small current by a method wherein a MOS-FET which is connected in parallel with a bipolar transistor is compounded in addition to a MOS-FET for driving the base of the bipolar transistor. CONSTITUTION:An n-p-n bipolar transistor 41 is composed of an n -type substrate 1, an n -type layer 2, a p -type layer 3 and an n -type layer 4. An n-type channel MOS-FET 51 is composed of the n -type layer 2, a first channel region 7 and an n -type layer 5. Further, a p-type channel MOS-FET 52 is composed of the p -type layer 3, a second channel region 8 and a p -type layer 6 and an n-type channel MOS-FET 53 is composed of the n-type layer 2, a third channel region 15 and the n -type layer 4. If a positive voltage is applied to the gates of the MOS-FET 51 and the MOS-FET 53 through a gate terminal G while a positive voltage is applied to the collector terminal C of such a semiconductor device, a current is made to flow between the collector terminal C and an emitter terminal E through the channel of the MOS-FET 53. Therefore, an ON-voltage is gradually increased. With this constitution, the fluctuation of the ON-voltage at the time of turning-ON can be smoothened.

10. 发明专利

JPH02100366A INSULATING GATE TYPE TRANSISTOR 失效
公开(公告)号：JPH02100366A
公开(公告)日：1990-04-12
申请号：JP25310488
申请日：1988-10-07
申请人： FUJI ELECTRIC CO LTD
发明人： NISHIURA AKIRA
IPC分类号： H01L29/68 , H01L29/739 , H01L29/78
摘要： PURPOSE:To prevent the ON-state resistance from increasing in a small current by forming an N diffusion layer in other part than a P layer on the surface of an N layer. CONSTITUTION:After an N layer 2 and an N layer 3 are formed on the surface of a P substrate 1, ions are selectively implanted to form N diffusion layers 11 after. Gate insulating films 6 are formed and then gate electrodes 7 are installed thereon. Ions are implanted with the gate electrodes 7 used as masks to form a P layer 4 after, the N diffusion layers 11 and the P layer 4 are formed simultaneously by thermal diffusion, N layers 5 are formed by ion implantation and thermal diffusion methods with the gate electrodes 7 used as masks, insulating films 10 are formed, and a source electrode 8 and a drain electrode 9 are formed. Thereby electrons implanted into a third layer through the channel area of a MOSFET run through a highly conductive sixth area, therefore, the ON-state resistance does not increase even in a little current.

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