专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明专利

JP2001250388A NON-VOLATILE MEMORY STORING ERASION OPERATION INFORMATION 失效
公开(公告)号：JP2001250388A
公开(公告)日：2001-09-14
申请号：JP2000060830
申请日：2000-03-06
申请人： FUJITSU LTD
发明人： OTANI HIROSHI , IGARASHI MAKOTO , TSUKIDATE YOSHIHIRO
IPC分类号： G06F12/16 , G11C16/02 , G11C16/16 , G11C16/34
摘要： PROBLEM TO BE SOLVED: To check whether erasion operation is finished normally for a memory block of a flash memory or not. SOLUTION: This memory is a non-volatile memory device having a normal memory cell region in which normal data is stored and an erasion information storing memory region in which information of whether a series of erasing operation is finished or not or information indicating a state of erasing operation is stored. The erasion information storing memory region is constituted of non-volatile memories so that the information can be held even if a power source is cut off. Preferably, erasion information of a memory block unit in which this erasing operation is performed can be stored in the erasion information storing memory region. Further preferably, erasion information about at least three states of an erasing operation start state, a pre-program finish state, and an erasing operation finish state in a series of erasing operation can be stored in the erasion information storing memory region.

2. 发明专利

JPH04119590A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH04119590A
公开(公告)日：1992-04-21
申请号：JP23966790
申请日：1990-09-10
申请人： FUJITSU LTD
发明人： TSUKIDATE YOSHIHIRO
IPC分类号： G11C11/417 , G11C11/409
摘要： PURPOSE:To drive wirings of large capacity load (global buses) at high speed by arranging a latch circuit between a sense amplifier and the global buses. CONSTITUTION:The CMOS latch circuit 12 is arranged between the sense amplifier 10 driving the global buses GB, -GB and the global buses GB, -GB. In this case, a CLK system is used for the operational signal (-BDC signal) for preventing the CMOS latch circuit 12 from latching before the output of sense amplifier 10 is opened to some extent (before the output becomes larger than a certain level). That is, when the output of sense amplifier 10 starts to open, the -BDC signal becomes the high level and switching elements 13, 16 in the latch circuit 12 become the ON state. Therefore, the CMOS latch circuit 12 becomes the operational state and the global buses GB, -GB are driven. Thus, the wirings GB, -GB of large capacity load can be driven at high speed.

3. 发明专利

JP2004110872A Nonvolatile semiconductor storage device 有权
公开(公告)号：JP2004110872A
公开(公告)日：2004-04-08
申请号：JP2002268317
申请日：2002-09-13
申请人： Fujitsu Ltd , 富士通株式会社
发明人： TSUKIDATE YOSHIHIRO
IPC分类号： G11C16/06 , G11C7/14 , G11C16/26 , G11C16/28
CPC分类号： G11C7/14 , G11C16/28
摘要： PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor storage device which can execute an adequate comparison operation between reference circuits and respective blocks in a configuration in which memory cell arrays are divided into a plurality of blocks. SOLUTION: The nonvolatile semiconductor storage device includes the plurality of blocks each of which includes one memory cell array, reference cells, signal lines which supply the reference signals read out of the reference cells to each of the plurality of blocks, reference load circuits which are disposed at the plurality of the respective blocks and impart the same load as the load applied to the read-out data from the memory cell arrays to the reference signals, and sense circuits which are disposed respectively at the plurality of respective blocks and decide the read-out data by comparing the reference signals applied with the load by the reference load circuits and the read-out data. COPYRIGHT: (C)2004,JPO

4. 发明专利

JPH0554699A TEST DEVICE FOR MEMORY INTEGRATED CIRCUIT 失效
公开(公告)号：JPH0554699A
公开(公告)日：1993-03-05
申请号：JP21240991
申请日：1991-08-23
申请人： FUJITSU LTD
发明人： TSUKIDATE YOSHIHIRO
IPC分类号： G06F11/22 , G06F12/16 , G11C29/00 , G11C29/56
摘要： PURPOSE:To easily pinpoint a faulty portion of a memory to be tested by outputting a strobe signal corresponding to the specific bit address change only which is designated by a bit storage section during a read control signal generation. CONSTITUTION:When all values given to a bit storage register are zero, a strobe signal generator 27 outputs a strobe signal STRB corresponding to each change of all address bits. When a value one is given to any one of the bits of the register, the generator outputs the signal STRB in accordance with the bit value of a change direction storage register and in response to the specific address bit change in the specific direction. When the subject address is specified, an address change takes place between the adjacent addresses and each time the data which are read and the expected value data are compared. When a result decision section 22 detects an existence of a failure, it is outputted to the address of a test result memory 21 and a sequence control section 15 and a pinpoint processing of faulty portion takes place.

5. 发明专利

JP2004103143A Memory circuit having redundancy constitution 审中-公开
公开(公告)号：JP2004103143A
公开(公告)日：2004-04-02
申请号：JP2002265065
申请日：2002-09-11
申请人： Fujitsu Ltd , 富士通株式会社
发明人： TSUKIDATE YOSHIHIRO , KURIHARA KAZUHIRO , RYU SEI , NAKAI TSUTOMU , ANDY CHEN
IPC分类号： G11C16/06 , G11C16/02 , G11C29/00 , G11C29/04 , G11C29/24
CPC分类号： G11C29/82 , G11C29/24 , G11C29/846
摘要： PROBLEM TO BE SOLVED: To provide a memory circuit with redundancy constitution in which a reduction in access speed caused by redundancy discrimination is suppressed. SOLUTION: In a memory circuit having a plurality of blocks having a plurality of regular sectors and spare sectors, each sector has a plurality of memory cells, when a regular sector in a first block is defective, the defective regular sector is replaced by a spare sector in a second block. And a spare sector in the second block is selected simultaneously with a regular sector corresponding to a selection address in the first block during a first period responding to a supplied address, after the first period, the selection of either of a regular sector or a spare sector is kept in accordance with a redundancy discrimination result of whether the supplied address coincides with a redundancy address or not. COPYRIGHT: (C)2004,JPO

6. 发明专利

JPH0832422A PULSE WIDTH EXPANSION CIRCUIT 失效
公开(公告)号：JPH0832422A
公开(公告)日：1996-02-02
申请号：JP16496094
申请日：1994-07-18
申请人： FUJITSU LTD
发明人： TSUKIDATE YOSHIHIRO
IPC分类号： G11C11/41 , G06F1/06 , G11C7/22 , G11C8/18 , G11C11/413 , H03K5/04 , H03K5/06 , H03K5/13
摘要： PURPOSE:To prevent a circuit of a next stage from malfunctioning by not outputting an output pulse signal obtained by expanding a pulse width of an input pulse signal when the pulse width of the input pulse signal is narrower than a prescribed width. CONSTITUTION:A delay circuit 20 delays an input pulse signal, and a pulse width detection circuit 21 detects a pulse width of the input pulse signal and outputs a pulse width detection signal only when the pulse width is a prescribed width or over. When an output pulse signal generating circuit 22 receives the pulse width detection signal from the pulse width detection circuit 21, the generating citcuit 22 inverts a potential at an output terminal 22A and holds the inverted potential, and when the generating circuit 22 receives the input pulse signal delayed by the delay circuit 20, the generating circuit 22 restores the potential at the output terminal 22A and holds it and outputs an output pulse signal whose pulse width is expacnded. That is, when the pulse width of the input pulse signal is narrower than the prescribed width, since the pulse width detection circuit 21 does not output the pulse width detection signal, the output pulse signal generating circuit 22 does not generate an output pulse.

7. 发明专利

JPH0529561A SEMICONDUCTOR INTEGRATED CIRCUIT 失效
公开(公告)号：JPH0529561A
公开(公告)日：1993-02-05
申请号：JP17925191
申请日：1991-07-19
申请人： FUJITSU LTD
发明人： MATSUOKA MASAMI , TSUKIDATE YOSHIHIRO
IPC分类号： H01L27/04 , G11C11/408 , H01L21/822 , H01L21/8238 , H01L27/092
摘要： PURPOSE:To prevent the latch up of a CMOS transistor in a semiconductor integrated circuit when power is turned on. CONSTITUTION:In this semiconductor integrated circuit provided with a functional circuit 3, a circuit 4 which generates back bias power to the circuit 3, and a supply line 1 for supplying power to the circuits 3 and 4, a delay supply circuit 2 which delays the power supply starting timing for actuating the circuit 3 than the power supply starting timing for actuating the circuit is incorporated.

8. 发明专利

JP2002151644A LAMINATED SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF 失效
公开(公告)号：JP2002151644A
公开(公告)日：2002-05-24
申请号：JP2001121539
申请日：2001-04-19
申请人： FUJITSU LTD
发明人： KIKUMA KATSUTO , IKEDA MITSUTAKA , TSUKIDATE YOSHIHIRO , AKASHI YUJI , OZAWA KANAME , TAKASHIMA AKIRA , UNO TADASHI , NISHIMURA TAKAO , ANDO FUMIHIKO , ONODERA HIROSHI , OKUDA ISATO
IPC分类号： H01L23/12 , H01L23/31 , H01L25/065 , H01L25/07 , H01L25/18
摘要： PROBLEM TO BE SOLVED: To provide a laminated semiconductor device, which can house arbitrary sizes of a plurality of semiconductor elements in one package in a state that the elements are laminated, and to provide the manufacturing method of the laminated semiconductor device. SOLUTION: A laminated semiconductor device is constituted in a structure that a first semiconductor element 22 is mounted on a flexible printed board 26 provided with terminals for external connection. A printed circuit board 32 is provided on the element 22, and the element 22 is flip-chip mounted on the board 26. A second semiconductor element 24 is fixed on the board 32. The element 24 is wire-bonded to the board 26 and the element 22 is wire- bonded to the board 26 via the board 32.

9. 发明专利

JPH05151074A SEMICONDUCTOR STORAGE DEVICE 失效
公开(公告)号：JPH05151074A
公开(公告)日：1993-06-18
申请号：JP31203991
申请日：1991-11-27
申请人： FUJITSU LTD
发明人： TSUKIDATE YOSHIHIRO
IPC分类号： G06F12/06
摘要： PURPOSE:To eliminate the need for data saving operation for transferring data which are written before to another memory area of the semiconductor storage device when the data are written in the memory, to write plural data in the same address, and to obtain high operation efficiency. CONSTITUTION:This semiconductor means 11 is provided with (n+1) storage parts 10 for each of addresses #0-#m and equipped with a data input/output control means 14 consisting of transfer gates 13 which control the input and output of data of the storage part 11 in WAY units. The data input/output control means 14 selects the specific transfer gate 13 through a decoder 16 according to the register data in a register (utilization state storage means) stored with the utilization state of the storage parts 10 corresponding to the respective addresses, stores the data while changing the storage parts 10 in order so that the data are not written in the same storage part 10, and takes them out.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式