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1. 发明专利

JP2007273624A Semiconductor device and its manufacturing method 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2007273624A
公开(公告)日：2007-10-18
申请号：JP2006095737
申请日：2006-03-30
申请人： Fujitsu Ltd , 富士通株式会社
发明人： SAITO NOBUKATSU , UNO TADASHI , KANO MASASHI , MATSUOKA YOSHIHIRO
IPC分类号： H01L21/3205 , H01L21/60 , H01L23/52
CPC分类号： H01L24/05 , H01L23/293 , H01L23/3192 , H01L24/03 , H01L24/13 , H01L2224/02166 , H01L2224/0345 , H01L2224/03912 , H01L2224/0401 , H01L2224/05012 , H01L2224/05086 , H01L2224/05095 , H01L2224/05124 , H01L2224/05571 , H01L2224/05573 , H01L2224/05666 , H01L2224/1146 , H01L2224/1147 , H01L2224/11849 , H01L2224/131 , H01L2924/0002 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01075 , H01L2924/01078 , H01L2924/01082 , H01L2924/014 , H01L2924/15787 , H01L2924/3025 , H01L2924/351 , H01L2924/00014 , H01L2924/01014 , H01L2224/05552 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device inhibiting the peeling of a wiring layer and a conductive layer due to a thermal stress at a time when a semiconductor substrate is mounted, preventing an electrical disconnection and having a high performance and a high reliability and an efficient manufacturing method for the semiconductor device. SOLUTION: The semiconductor device has the semiconductor substrate (such as a silicon wafer 10), the wiring layer 14 formed on the semiconductor substrate 10 and a first conductive layer 15 formed on the wiring layer. The semiconductor device further has an inter-layer insulating film 16 formed on the first conductive layer and a second conductive layer 17 formed on the inter-layer insulating film 16 in a conductible manner with the first conductive layer 15. A bump is formed on the second conductive layer. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：解决的问题：为了提供一种半导体器件，其在安装半导体衬底时由于热应力而抑制布线层和导电层的剥离，防止电断开并具有高性能和高可靠性和半导体器件的高效制造方法。解决方案：半导体器件具有半导体衬底（例如硅晶片10），形成在半导体衬底10上的布线层14和形成在布线层上的第一导电层15。半导体器件还具有形成在第一导电层上的层间绝缘膜16和与第一导电层15以可导电的方式形成在层间绝缘膜16上的第二导电层17。第二导电层。版权所有（C）2008，JPO＆INPIT

2. 发明专利

JP2004214403A Stacked semiconductor device 有权
标题翻译：堆叠半导体器件
公开(公告)号：JP2004214403A
公开(公告)日：2004-07-29
申请号：JP2002382046
申请日：2002-12-27
申请人： Fujitsu Ltd , 富士通株式会社
发明人： NISHIMURA TAKAO , UNO TADASHI , TAKASHIMA AKIRA
IPC分类号： H01L25/18 , H01L25/065 , H01L25/07
CPC分类号： H01L2224/32145 , H01L2224/32225 , H01L2224/48227 , H01L2224/73265 , H01L2924/15311 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To reduce the occurrence of any crack at a circuit board in a stacked semiconductor device.
SOLUTION: The stacked semiconductor device is provided with a first circuit board 12 having a semiconductor element 18, a second circuit board 14 stacked under the first circuit board 12 and having a semiconductor element 26, and a plurality of electrode terminals 24 electrically connecting the first circuit board 12 with the second circuit board 14. The outline of the second circuit board 14 is formed to be larger than that of the first circuit board 12 to house the outline of the second circuit board 14 within the range of that of the first circuit board 12. In the area outside of the second circuit board 14 of the first circuit board 12, the electrode terminals are not arranged.
COPYRIGHT: (C)2004,JPO&NCIPI
摘要翻译：要解决的问题：为了减少层叠半导体器件中的电路板处的任何裂纹的发生。解决方案：堆叠半导体器件设置有第一电路板12，其具有半导体元件18，第二电路板14，第二电路板14堆叠在第一电路板12下方并具有半导体元件26，以及多个电极端子24电将第一电路板12与第二电路板14连接。第二电路板14的轮廓形成为大于第一电路板12的轮廓，以将第二电路板14的轮廓容纳在第二电路板14的轮廓范围内第一电路板12.在第一电路板12的第二电路板14之外的区域中，不布置电极端子。版权所有（C）2004，JPO＆NCIPI

3. 发明专利

JPH08116022A SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE UNIT 失效
公开(公告)号：JPH08116022A
公开(公告)日：1996-05-07
申请号：JP31102194
申请日：1994-12-14
申请人： FUJITSU LTD
发明人： UNO TADASHI , SATO MITSUTAKA , YOSHIMURA HIROSHI , HAYASHIDA KATSUHIRO , OKITA KOSUKE , FUJISAWA TETSUYA
IPC分类号： H01L25/00 , H01L25/10 , H01L25/11 , H01L25/18
摘要： PURPOSE: To improve the packaging capacity, the maintainability and heat radiating capacity in relation to the semiconductor device and semiconductor device unit packaged in almost vertical state to a package substrate. CONSTITUTION: The semiconductor device unit 50 is formed of semiconductor devices 10 formed of a stage 13 whereon upward extending parts 17 extending upward from the surface of resin packages 15, a holder 51 having an upper part aperture part 53 simultaneously containing semiconductor devices 10 in the juxtaposed state as well as a cap 52 in contact with the upward extending parts 17 formed on the semiconductor devices 10 in the open state of the upper part aperture part 53.

4. 发明专利

JP2008047699A Semiconductor device and its manufacturing method 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2008047699A
公开(公告)日：2008-02-28
申请号：JP2006221953
申请日：2006-08-16
申请人： Fujitsu Ltd , 富士通株式会社
发明人： UNO TADASHI , SAITO NOBUKATSU
IPC分类号： H01L23/29 , H01L21/56 , H01L23/31
CPC分类号： H01L23/3128 , H01L23/3135 , H01L24/45 , H01L24/48 , H01L2224/45144 , H01L2224/48091 , H01L2924/00014 , H01L2924/01019 , H01L2924/01078 , H01L2924/01079 , H01L2924/15311 , H01L2924/181 , H01L2924/00012 , H01L2224/45015 , H01L2924/207
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device which distributes a stress generated on a boundary between the end of a sealing resin and a wiring board, and suppresses the generation of a crack in the wiring board, and also to provide a manufacturing method for the semiconductor device. SOLUTION: The semiconductor device 40 has a structure resin-sealing a semiconductor element 35 formed on the wiring board 41 by the sealing resin 42-1. In the semiconductor device 40, a reinforcing resin 42-2 different from the sealing resin 42-1 is formed in at least a part of the boundary with the wiring board 41. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：解决的问题：提供一种半导体装置，其分布在密封树脂的端部与布线基板的端部之间的边界上产生的应力，并且抑制布线板中的裂纹的产生，并且还提供半导体器件的制造方法。解决方案：半导体器件40具有通过密封树脂42-1树脂密封形成在布线板41上的半导体元件35的结构。在半导体装置40中，在与布线基板41的边界的至少一部分上形成与密封树脂42-1不同的增强树脂42-2。（C）2008，JPO＆INPIT

5. 发明专利

JP2001319988A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JP2001319988A
公开(公告)日：2001-11-16
申请号：JP2000133763
申请日：2000-05-02
申请人： FUJITSU LTD
发明人： UNO TADASHI , TAKASHIMA AKIRA
IPC分类号： H01L23/28 , H01L23/12 , H01L23/52
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device that has a simple configuration applying the structure of a package with a conventional chip size and a small packaging area, and can be vertically packaged for the semiconductor device where a package is vertically arranged to a packaging substrate for reducing the packaging area. SOLUTION: A semiconductor chip 6 is mounted onto a first surface 4a where the wiring pattern of a flexible circuit substrate 4 is formed. A solder ball 8 is formed on a second surface 4b at a side opposite to the first surface. The semiconductor chip 6 is resin-sealed to form a sealing part 10. The side of the surface 4a where the soldering ball 8 is formed is resin-sealed to form a sealing part 12. The circuit substrate 4 is bent for bonding the sealing part 12 to the sealing part 10.

6. 发明专利

JP2001274187A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JP2001274187A
公开(公告)日：2001-10-05
申请号：JP2000082734
申请日：2000-03-23
申请人： FUJITSU LTD
发明人： TANIGUCHI FUMIHIKO , TAKASHIMA AKIRA , UNO TADASHI
IPC分类号： H01L23/12 , H01L21/60
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device which can be enhanced in electrical characteristics and assembled at a low cost. SOLUTION: A semiconductor device is equipped with an interposer 14, which is mounted with a semiconductor chip 12 and equipped with bonding pads and ball lands, wires 16 which connect the electrode pads of the semiconductor chip 12 to the bonding pads of the interposer 14, and conductive balls connected to the ball lands of the interposer 14, where the bonding pads and ball lands are formed as conductive pieces 24 and 26 in common. One conductive piece comprising the bonding pad and ball land and the other conductive piece comprising the bonding pad and ball land are arranged to confront each other, so that a semiconductor device of this constitution is capable of coping with signals which need high-speed transmission.

7. 发明专利

JPH0897347A LEAD MEMBER, SEMICONDUCTOR DEVICE, ITS MANUFACTURE AND SEMICONDUCTOR MODULE 失效
公开(公告)号：JPH0897347A
公开(公告)日：1996-04-12
申请号：JP22979294
申请日：1994-09-26
申请人： FUJITSU LTD
发明人： MIYAJI NAOKI , UNO TADASHI , FUJISAWA TETSUYA , MIZUKOSHI MASATAKA , SONO RIKURO
IPC分类号： H01L21/60 , H01L23/50
摘要： PURPOSE: To downsize a semiconductor device by downsizing the lead member which includes film carrier tape. CONSTITUTION: A lead member is provided with a plurality of inner leads 12a for electrical connection with electrodes, according to the positions of a plurality of electrodes of a semiconductor chip, and a plurality of outer leads 12c which continuously extend from each inner lead 12a. Middle leads 12b are provided between the inner leads and the outer leads on middle lead resin tape 11a so as to direct a plurality of outer leads 12c extended from a plurality of inner leads 12a to one side of the semiconductor chip.

8. 发明专利

JP2007318183A Multilayer semiconductor device 审中-公开
标题翻译：多层半导体器件
公开(公告)号：JP2007318183A
公开(公告)日：2007-12-06
申请号：JP2007228247
申请日：2007-09-03
申请人： Fujitsu Ltd , 富士通株式会社
发明人： NISHIMURA TAKAO , UNO TADASHI , TAKASHIMA AKIRA
IPC分类号： H01L25/10 , H01L25/065 , H01L25/07 , H01L25/11 , H01L25/18
CPC分类号： H01L25/0657 , H01L2224/48225 , H01L2224/48227 , H01L2924/15311 , H01L2924/15331
摘要： PROBLEM TO BE SOLVED: To reduce occurrence of cracks in a wiring substrate in relation to a multilayer semiconductor device. SOLUTION: The multilayer semiconductor device comprises a primary wiring substrate 12 with a semiconductor element 18, a secondary wiring substrate 14 which is laminated under the primary wiring substrate 12 and has a semiconductor element 26, and two or more electrode terminals 24 which electrically connect the primary wiring substrate 12 and the secondary wiring substrate 14. The dimension of the primary wiring substrate 12 is larger than that of the secondary wiring substrate 14 so that the outline of the secondary wiring substrate 14 is included within the area enclosed by the outline of the primary wiring substrate 12. The electrode terminals are not placed in the area of the primary wiring substrate 12 outside the secondary wiring substrate 14. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：为了减少布线基板中相对于多层半导体器件的裂纹的发生。解决方案：多层半导体器件包括具有半导体元件18的初级布线基板12，层叠在初级布线基板12下方并具有半导体元件26的二次布线基板14以及两个或更多个电极端子24 将一次布线基板12和二次布线基板14电连接。一次布线基板12的尺寸大于二次布线基板14的尺寸，使得二次布线基板14的轮廓包含在由初级布线基板12的轮廓。电极端子不被放置在次级布线基板14的外侧的一次布线基板12的区域中。（C）2008，JPO＆INPIT

9. 发明专利

JP2004165283A Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：JP2004165283A
公开(公告)日：2004-06-10
申请号：JP2002327091
申请日：2002-11-11
申请人： Fujitsu Ltd , 富士通株式会社
发明人： NISHIMURA TAKAO , ONODERA HIROSHI , UNO TADASHI , TAKASHIMA AKIRA
IPC分类号： H01L25/18 , H01L21/60 , H01L25/065 , H01L25/07
CPC分类号： H01L2224/48091 , H01L2224/48227 , H01L2224/73204 , H01L2224/83192 , H01L2924/01079 , H01L2924/15311 , H01L2924/00014
摘要： PROBLEM TO BE SOLVED: To avoid undesirable adhesion of underfill resin to a part except for a prescribed part even if thickness of a first semiconductor chip is 150μm or thinner and to improve efficiency and reliability of a process in a semiconductor device in which second and subsequent semiconductor chips are sequentially mounted on a first semiconductor chip which is bump-connected to a circuit board.
SOLUTION: Sides of the first semiconductor chip and the second semiconductor chip are prevented from being covered by resin obtained by extending a part of underfill resin packed between the first semiconductor chip and the circuit board.
COPYRIGHT: (C)2004,JPO
摘要翻译：要解决的问题：即使第一半导体芯片的厚度为150μm以下，为了避免底部填充树脂对除了规定部分以外的部分的不良粘合，并且为了提高半导体装置中的工序的效率和可靠性，其中第二和随后的半导体芯片依次安装在凸块连接到电路板的第一半导体芯片上。解决方案：通过将填充在第一半导体芯片和电路板之间的一部分底部填充树脂延伸而获得的树脂被防止被第一半导体芯片和第二半导体芯片的侧面覆盖。版权所有（C）2004，JPO

10. 发明专利

JPH11274192A Die for manufacture of semiconductor device 失效
标题翻译：用于制造半导体器件的DIE
公开(公告)号：JPH11274192A
公开(公告)日：1999-10-08
申请号：JP7287998
申请日：1998-03-20
申请人： Fujitsu Ltd , 富士通株式会社
发明人： NIIMA YASUHIRO , MORIOKA MUNETOMO , FUKAZAWA NORIO , HAMANAKA YUZO , UNO TADASHI , MATSUKI HIROHISA , NAGAE KENICHI
IPC分类号： H01L21/56 , B29C43/18 , B29C43/36
CPC分类号： B29C43/36 , B29C43/18 , B29C2043/5858 , H01L21/565 , H01L2924/0002 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a die so as to always maintain the parallelism at high accuracy between an upper and lower dies, irrespective of the accuracy of a pressuring apparatus regarding the semiconductor device manufacturing dies used for the resin encapsulation of a semiconductor element, using compression molding method.
SOLUTION: In a semiconductor device manufacturing die in which a semiconductor element 15 and encapsulating resin 16 are inserted between an upper and lower dies 11, 12, an encapsulating resin 16 is compression-molded to form an encapsulating resin layer on the semiconductor element 16 using a pressuring apparatus, the upper die 11 has a top fixed plate 20 which is foxed to the pressuring apparatus and a press plate 23 for pressing the encapsulating resin 16 and also has a floating structure such that the press plate 23 is supported shiftably in the rotting and horizontal directions.
COPYRIGHT: (C)1999,JPO
摘要翻译：要解决的问题：为了提供一种模具，以便在与半导体元件的树脂封装所使用的半导体器件制造用模具的加压装置的精度无关地在上下模具之间保持高精度的平行度，采用压缩成型法。解决方案：在将半导体元件15和封装树脂16插入在上模11和下模12之间的半导体器件制造裸片中，将密封树脂16压缩成型以在半导体元件16上形成密封树脂层，使用加压装置，上模具11具有顶部固定板20，该固定板20被压在加压装置上，压板23用于按压封装树脂16，并且还具有浮动结构，使得压板23可移动地支撑在腐烂状态和水平方向。

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