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1. 发明专利

JP2004288260A Semiconductor memory device 有权
公开(公告)号：JP2004288260A
公开(公告)日：2004-10-14
申请号：JP2003076960
申请日：2003-03-20
申请人： Fujitsu Ltd , 富士通株式会社
发明人： NAKAI TSUTOMU
IPC分类号： G11C16/06 , G11C16/02 , G11C16/04
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor memory device capable of simply and easily controlling the setting of a reference memory cell when a value stored in a core memory cell is determined based on the reference memory cell. SOLUTION: This semiconductor memory device is provided with one or more core memory cells 401 capable of storing n (n is an integer of 3 or more) values, reference memory cells 411 to 413 for storing the n values and m (m is an integer of 1 to n-1) values, and determination circuits 431 to 433 for determining values stored in the core memory cells based on the read outputs of the reference memory cells. COPYRIGHT: (C)2005,JPO&NCIPI

2. 发明专利

JP2004110881A Semiconductor memory 有权
标题翻译：半导体存储器
公开(公告)号：JP2004110881A
公开(公告)日：2004-04-08
申请号：JP2002268606
申请日：2002-09-13
申请人： Fujitsu Ltd , 富士通株式会社
发明人： NAKAI TSUTOMU , YAMASHITA MINORU , ANDY CHEN , KURIHARA KAZUHIRO
IPC分类号： G11C16/06 , G11C16/04
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor memory capable of correctly reading data in a core cell with a large margin. SOLUTION: The semiconductor memory is provided with the core cell 11, at least one internal reference cell 12, 13 arranged within the area of core cell, at least one external reference cell 50 arranged outside the core cell, and a reference voltage generation circuit 40 for generating the reference voltage Vref by using at least one of the internal reference cells and at least one external reference cell jointly at the same time. The reference voltage generation circuit is provided with switch circuits 41, 42 for controlling the connections between the internal reference cells and the external reference cells and a control circuit 43 for controlling the switch circuits, and is configured so as to read the data stored in the core cell by using the output of the reference voltage generation circuit. COPYRIGHT: (C)2004,JPO
摘要翻译：要解决的问题：提供能够以大幅度正确读取核心单元中的数据的半导体存储器。解决方案：半导体存储器设置有核心单元11，布置在核心单元的区域内的至少一个内部参考单元12,13，布置在核心单元外部的至少一个外部参考单元50以及参考电压生成电路40，用于通过同时使用内部参考单元和至少一个外部参考单元中的至少一个来产生参考电压Vref。参考电压产生电路设置有用于控制内部参考单元和外部参考单元之间的连接的开关电路41,42和用于控制开关电路的控制电路43，并且被配置为读取存储在使用参考电压产生电路的输出。版权所有（C）2004，JPO

3. 发明专利

JP2004103143A Memory circuit having redundancy constitution 审中-公开
公开(公告)号：JP2004103143A
公开(公告)日：2004-04-02
申请号：JP2002265065
申请日：2002-09-11
申请人： Fujitsu Ltd , 富士通株式会社
发明人： TSUKIDATE YOSHIHIRO , KURIHARA KAZUHIRO , RYU SEI , NAKAI TSUTOMU , ANDY CHEN
IPC分类号： G11C16/06 , G11C16/02 , G11C29/00 , G11C29/04 , G11C29/24
CPC分类号： G11C29/82 , G11C29/24 , G11C29/846
摘要： PROBLEM TO BE SOLVED: To provide a memory circuit with redundancy constitution in which a reduction in access speed caused by redundancy discrimination is suppressed. SOLUTION: In a memory circuit having a plurality of blocks having a plurality of regular sectors and spare sectors, each sector has a plurality of memory cells, when a regular sector in a first block is defective, the defective regular sector is replaced by a spare sector in a second block. And a spare sector in the second block is selected simultaneously with a regular sector corresponding to a selection address in the first block during a first period responding to a supplied address, after the first period, the selection of either of a regular sector or a spare sector is kept in accordance with a redundancy discrimination result of whether the supplied address coincides with a redundancy address or not. COPYRIGHT: (C)2004,JPO

4. 发明专利

JP2003045196A Memory circuit having block address switching function 审中-公开
标题翻译：具有块地址切换功能的存储器电路
公开(公告)号：JP2003045196A
公开(公告)日：2003-02-14
申请号：JP2001234664
申请日：2001-08-02
申请人： Fujitsu Ltd , 富士通株式会社
发明人： IKEDA MITSUTAKA , NAKAI TSUTOMU , YAMASHITA KOJI , KURITA TOSHIYUKI
IPC分类号： G06F12/16 , G11C16/06 , G11C29/00 , G11C29/04
CPC分类号： G11C29/76 , G11C29/88
摘要： PROBLEM TO BE SOLVED: To relieve a defective memory cell by using effectively a memory cell region in a chip and to enable accessing by varying sequentially an address from the outside even when relieving the defective memory cell. SOLUTION: In a memory circuit in which a defective cell can be relieved, the circuit has a plurality of memory blocks MB having respectively a plurality of memory cells, a region 16 storing a block address of a defective memory block having a defective cell, and a comparison circuit comparing a block address to be accessed with a block address of a defective memory block and detecting access to the defective memory block. And when the comparison circuit detects access to the defective memory block, the defective memory block is replaced by a memory block of the highest order address (or the lowest order address) out of a plurality of the memory blocks. When a plurality of defective memory blocks exist, they are replaced successively from the most significant bit (or the least significant bit) as switching memory blocks.
摘要翻译：要解决的问题：为了通过有效利用芯片中的存储单元区域来缓解有缺陷的存储单元，并且即使在释放有缺陷的存储单元时也能够通过依次改变来自外部的地址来访问。解决方案：在可以消除缺陷单元的存储器电路中，电路具有分别具有多个存储单元的多个存储块MB，存储具有缺陷单元的缺陷存储块的块地址的区域16，以及将待访问的块地址与有缺陷的存储块的块地址进行比较并检测对缺陷存储块的访问的比较电路。并且当比较电路检测到对缺陷存储块的访问时，由多个存储块中的最高地址（或最低位地址）的存储块替换有缺陷的存储块。当存在多个有缺陷的存储块时，它们被从最高有效位（或最低有效位）连续替换为切换存储器块。

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