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1. 发明专利

JP2008227050A Wiring substrate and electronic component mounting structure 有权
标题翻译：接线基板和电子元件安装结构
公开(公告)号：JP2008227050A
公开(公告)日：2008-09-25
申请号：JP2007061531
申请日：2007-03-12
申请人： Fujitsu Ltd , 富士通株式会社
发明人： NISHIMURA TAKAO
IPC分类号： H01L21/60 , H01L23/12
CPC分类号： H05K1/111 , H01L23/49838 , H01L24/11 , H01L24/13 , H01L24/32 , H01L24/80 , H01L24/81 , H01L2224/0557 , H01L2224/05571 , H01L2224/05573 , H01L2224/05624 , H01L2224/05644 , H01L2224/05647 , H01L2224/11 , H01L2224/1134 , H01L2224/13 , H01L2224/13099 , H01L2224/13144 , H01L2224/13147 , H01L2224/1411 , H01L2224/16225 , H01L2224/27013 , H01L2224/32225 , H01L2224/73204 , H01L2224/81193 , H01L2224/81194 , H01L2224/8121 , H01L2224/81385 , H01L2224/814 , H01L2224/81815 , H01L2224/83051 , H01L2224/83385 , H01L2224/83855 , H01L2224/92125 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01023 , H01L2924/01029 , H01L2924/01033 , H01L2924/01037 , H01L2924/0105 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01084 , H01L2924/01088 , H01L2924/0132 , H01L2924/014 , H01L2924/09701 , H01L2924/10329 , H01L2924/14 , H01L2924/15787 , H01L2924/15788 , H01L2924/1579 , H01L2924/15798 , H05K3/3436 , H05K3/3452 , H05K2201/09272 , H05K2201/09381 , H05K2201/09709 , H05K2201/09772 , H05K2201/0979 , H05K2201/0989 , H05K2201/10674 , Y02P70/611 , H01L2924/01031 , H01L2924/00 , H01L2924/00012 , H01L2924/00014 , H01L2924/013
摘要： PROBLEM TO BE SOLVED: To provide a wiring substrate on which an electronic component such as a semiconductor element is mounted via a conductive member and a structure for mounting the electronic component on the wiring substrate which realize a highly reliable mounting structure in which the connection stability (yield) of a convex outer connection terminal of the electronic component and a conductive layer of the wiring substrate is improved. SOLUTION: In a wiring substrate 11 on one principal surface of which a plurality of electrode terminals 16 to which an outer connection terminal 14 of an electronic component 12 is connected are arranged in line, the electrode terminal 16 has a first straight line-shaped portion 16-1, a second straight line-shaped portion 16-2 extending in a direction different from that of the first straight line-shaped portion 16-1 at the end of the first straight line-shaped portion 16-1, and a bending portion 16-3 in a portion in which the first straight line-shaped portion 16-1 and the second straight line-shaped portion 16-2 are continuous with each other. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：为了提供一种布线基板，其上经由导电部件安装诸如半导体元件的电子部件的布线基板和用于将电子部件安装在布线基板上的结构，其实现了高度可靠的安装结构，其中电子部件的凸形外部连接端子和布线基板的导电层的连接稳定性（屈服）提高。解决方案：在一个主表面上布置有多个电子部件12的外部连接端子14连接到其上的电极端子16的布线基板11中，电极端子16具有第一直线形状部分16-1，在第一直线状部分16-1的端部处沿与第一直线状部分16-1的方向不同的方向延伸的第二直线状部分16-2，以及在第一直线状部16-1和第二直线状部16-2彼此连续的部分中的弯曲部16-3。版权所有（C）2008，JPO＆INPIT

2. 发明专利

JP2008034567A Semiconductor device and manufacturing method therefor 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2008034567A
公开(公告)日：2008-02-14
申请号：JP2006205381
申请日：2006-07-27
申请人： Fujitsu Ltd , 富士通株式会社
发明人： NISHIMURA TAKAO , NARISAWA YOSHIAKI
IPC分类号： H01L21/60 , H01L25/065 , H01L25/07 , H01L25/18
CPC分类号： H01L23/3128 , H01L23/4952 , H01L23/49575 , H01L24/29 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L24/78 , H01L24/85 , H01L25/0657 , H01L2224/0401 , H01L2224/05553 , H01L2224/05624 , H01L2224/05647 , H01L2224/2919 , H01L2224/32145 , H01L2224/32225 , H01L2224/32245 , H01L2224/45015 , H01L2224/45124 , H01L2224/45139 , H01L2224/45144 , H01L2224/45147 , H01L2224/4809 , H01L2224/48091 , H01L2224/4813 , H01L2224/48145 , H01L2224/48227 , H01L2224/48247 , H01L2224/48465 , H01L2224/48471 , H01L2224/48475 , H01L2224/48479 , H01L2224/48482 , H01L2224/48487 , H01L2224/48499 , H01L2224/48624 , H01L2224/48647 , H01L2224/48724 , H01L2224/48747 , H01L2224/48824 , H01L2224/48847 , H01L2224/4899 , H01L2224/48992 , H01L2224/4911 , H01L2224/49112 , H01L2224/4917 , H01L2224/49426 , H01L2224/49429 , H01L2224/4945 , H01L2224/73265 , H01L2224/78301 , H01L2224/85045 , H01L2224/85051 , H01L2224/85186 , H01L2224/85191 , H01L2224/85205 , H01L2224/85206 , H01L2224/85951 , H01L2224/85986 , H01L2224/92247 , H01L2225/06506 , H01L2225/0651 , H01L2225/06527 , H01L2225/06562 , H01L2225/06572 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01029 , H01L2924/01031 , H01L2924/01033 , H01L2924/01047 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01083 , H01L2924/014 , H01L2924/09701 , H01L2924/10253 , H01L2924/10329 , H01L2924/12041 , H01L2924/15311 , H01L2924/181 , H01L2924/19107 , H01L2924/20751 , H01L2924/20752 , H01L2924/20753 , H01L2924/30105 , H01L2224/85181 , H01L2924/0665 , H01L2924/07025 , H01L2924/0635 , H01L2924/00 , H01L2924/00012 , H01L2224/48455 , H01L2224/4554
摘要： PROBLEM TO BE SOLVED: To provide a samll high performance semiconductor device capable of preventing contact between adjacent wires having high flexibility of wire connection, and to provide its effective manufacturing method. SOLUTION: The semiconductor device comprises a substrate 10 with an electrode 21 arranged on its surface, and a first semiconductor element 11A with an electrode 22 arranged on its surface and supported by the substrate 10. A first wire 41 is connected, to at least one electrode (at leat any of an electrode 21 and an electrode 22) arranged on at least any of the substrate 10 and the first semiconductor element 11A via a first bump 31, and a second wire 42 is connected to a part to be connected to the first wire 41 via a second bump 32. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供一种能够防止具有高的线连接灵活性的相邻线之间的接触的同质高性能半导体器件，并提供其有效的制造方法。解决方案：半导体器件包括其表面上布置有电极21的基板10，以及第一半导体元件11A，其表面上布置有电极22，并由基板10支撑。第一导线41连接到通过第一凸块31布置在基板10和第一半导体元件11A中的至少任一个上的至少一个电极（在电极21和电极22中的任何一个上）和第二导线42连接到一部分通过第二凸起32连接到第一导线41.版权所有（C）2008，JPO和INPIT

3. 发明专利

JP2007043065A Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：JP2007043065A
公开(公告)日：2007-02-15
申请号：JP2006061759
申请日：2006-03-07
申请人： Fujitsu Ltd , 富士通株式会社
发明人： NISHIMURA TAKAO , KUMAGAI KINICHI , TAKASHIMA AKIRA , NAKAMURA KOICHI , AIBA KAZUYUKI
IPC分类号： H01L21/60 , H01L25/065 , H01L25/07 , H01L25/18
CPC分类号： H01L23/3128 , H01L21/563 , H01L23/49811 , H01L23/49833 , H01L24/13 , H01L24/17 , H01L24/45 , H01L24/48 , H01L24/73 , H01L24/81 , H01L25/0657 , H01L2224/05001 , H01L2224/05022 , H01L2224/05124 , H01L2224/05147 , H01L2224/05568 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/05664 , H01L2224/05666 , H01L2224/05684 , H01L2224/1134 , H01L2224/13027 , H01L2224/13099 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/1411 , H01L2224/16145 , H01L2224/16225 , H01L2224/16227 , H01L2224/17107 , H01L2224/32145 , H01L2224/32225 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/48227 , H01L2224/48465 , H01L2224/73203 , H01L2224/73204 , H01L2224/73207 , H01L2224/73265 , H01L2224/81193 , H01L2224/81194 , H01L2224/81203 , H01L2224/81801 , H01L2225/06558 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01022 , H01L2924/01023 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/01049 , H01L2924/0105 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/09701 , H01L2924/10329 , H01L2924/12041 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/19042 , H01L2924/30107 , H01L2924/351 , H01L2924/00014 , H01L2924/00012 , H01L2924/00 , H01L2924/00015 , H01L2224/05541 , H01L2224/05005
摘要： PROBLEM TO BE SOLVED: To provide the arrangement structure of convex-shaped external connection terminals, in which the electrical connection between the convex-shaped external connection terminals of a semiconductor element and a conductive layer on a support substrate can be prevented from being cut off due to the concentration of stress, based on the difference in the thermal expansion coefficients between the semiconductor element and the support substrate on which a semiconductor substrate is mounted into a conductive member part between the convex-shaped external connection terminals of the semiconductor and the conductive layer on the support substrate. SOLUTION: A plurality of external connection terminal pads 102 are arranged on one main surface of the semiconductor substrate 101, and a plurality of convex-shaped external connection terminals 103A, 103B are arranged on these external connection pads 102. Since the plurality of convex-shaped external connection terminals are arranged, the contact area with a connection member is increased, between the convex-shaped external connection terminals on the semiconductor element and the conductive layer formed on the support substrate, and thereby stress generated due to temperature rise/fall is scattered over a wider range. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：为了提供凸形外部连接端子的布置结构，其中可以防止半导体元件的凸形外部连接端子与支撑基板上的导电层之间的电连接由于半导体元件和半导体衬底上的半导体衬底的支撑衬底之间的热膨胀系数的差异而导致的半导体器件的凸形外部连接端子之间的导体部件中的导电构件部分之间的应力集中而被切断和支撑基板上的导电层。解决方案：多个外部连接端子焊盘102布置在半导体衬底101的一个主表面上，并且多个凸形外部连接端子103A，103B布置在这些外部连接焊盘102上。由于多个设置凸形外部连接端子，与半导体元件上的凸形外部连接端子和形成在支撑基板上的导电层之间的连接构件的接触面积增大，由此由于温度升高而产生的应力 /落在更广泛的范围内。版权所有（C）2007，JPO＆INPIT

4. 发明专利

JP2006261549A Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：JP2006261549A
公开(公告)日：2006-09-28
申请号：JP2005079603
申请日：2005-03-18
申请人： Fujitsu Ltd , 富士通株式会社
发明人： NISHIMURA TAKAO , TAKASHIMA AKIRA , KOSAKAI KAZUNARI
IPC分类号： H01L23/12
CPC分类号： H01L2224/48227 , H01L2224/48228
摘要： PROBLEM TO BE SOLVED: To provide a surface-mounting semiconductor device whose joint with a mounting substrate can be confirmed visibly. SOLUTION: Generally, a semiconductor device is constructed so that a joining surface other than an external connection terminal 22 is covered with a solder resist 32. In the semiconductor device, however, because the solder resist 32 is not located in an area from the edge of a substrate 10 to the external connection terminal 22, the joint between the external terminal 22 and the mounting substrate can be observed from the side in a state that the semiconductor device is mounted on the mounting substrate. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供一种能够可靠地确认与安装基板的接合部的表面安装半导体装置。解决方案：通常，半导体器件被构造成使得除了外部连接端子22之外的接合表面被阻焊剂32覆盖。然而，在半导体器件中，由于阻焊剂32不位于区域从基板10的边缘到外部连接端子22，在半导体器件安装在安装基板上的状态下，可以从侧面观察外部端子22与安装基板之间的接合。版权所有（C）2006，JPO＆NCIPI

5. 发明专利

JP2006245319A Semiconductor device and semiconductor chip 有权
标题翻译：半导体器件和半导体芯片
公开(公告)号：JP2006245319A
公开(公告)日：2006-09-14
申请号：JP2005059387
申请日：2005-03-03
申请人： Fujitsu Ltd , 富士通株式会社
发明人： NISHIMURA TAKAO , KASHU MASANORI , AIBA KAZUYUKI , TAKASHIMA AKIRA
IPC分类号： H01L23/12
CPC分类号： H01L24/73 , H01L2224/16225 , H01L2224/4824 , H01L2224/73207 , H01L2224/73215 , H01L2924/15311 , H01L2924/30107 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To suppress IR drop when feeding power to a semiconductor chip having input/output electrode pads with an external circuit provided highly densely in its periphery.
SOLUTION: A semiconductor device includes a semiconductor chip 1 having a plurality of first electrode pads 2 provided around a principal plane of a semiconductor substrate, and at least one second electrode pad 3 provided on a region inside the first electrode pad 2; and a wiring board 4 having an opening 7 and a first bonding pad 5 for connecting to the first electrode pad 2 provided on the principal plane, and a second bonding pad 8 for connecting to the second electrode pad 3 provided on the opposite plane. The principal planes of the semiconductor chip 1 and the wiring board 4 are oppositely placed. The first electrode pad 2 is connected to the first bonding pad 5 with its face downward, and the second electrode pad 3 is connected through the opening 7 with the second bonding pad 8 by a bonding wire.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：为了在具有输入/输出电极焊盘的半导体芯片供电时抑制IR降低，外部电路在其外围高密度地设置。解决方案：半导体器件包括半导体芯片1，半导体芯片1具有围绕半导体衬底的主平面设置的多个第一电极焊盘2和设置在第一电极焊盘2内的区域上的至少一个第二电极焊盘3; 以及具有开口7的布线板4和用于连接到设置在主平面上的第一电极焊盘2的第一焊盘5和用于连接到设置在相对平面上的第二电极焊盘3的第二焊盘8。半导体芯片1和布线板4的主平面相对放置。第一电极焊盘2以面向下方的方式与第一接合焊盘5连接，第二电极焊盘3通过开口7与第二接合焊盘8通过接合线连接。版权所有（C）2006，JPO＆NCIPI

6. 发明专利

JP2005317860A Resin sealed semiconductor device 有权
标题翻译：树脂密封半导体器件
公开(公告)号：JP2005317860A
公开(公告)日：2005-11-10
申请号：JP2004136249
申请日：2004-04-30
申请人： Fujitsu Ltd , 富士通株式会社
发明人： KUMAGAI KINICHI , NISHIMURA TAKAO , TAKASHIMA AKIRA , AIBA KAZUYUKI
IPC分类号： H01L23/28 , H01L21/60
CPC分类号： H01L2224/05553 , H01L2224/0603 , H01L2224/451 , H01L2224/48 , H01L2224/4813 , H01L2224/48463 , H01L2224/49175 , H01L2924/181 , H01L2924/351 , H01L2924/00 , H01L2924/00012
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device which can maintain the heat resistance by improving the adhesion between a semiconductor element and a sealing resin covering it, or by reinforcing a part having the deficiency in adhesion. SOLUTION: The semiconductor element 2 has first electrode pads 4 connected by bonding wires 6 on the surface. The semiconductor element 2 and the bonding wires 6 are sealed by resin. The semiconductor element 2 also has second electrode pads 4A different from the first ones 4 on the surface. The second electrode pads 4A are ones not electrically connected to the outside when the semiconductor element 2 is assembled in the semiconductor device. On the second electrode pads 4A, bumps are bonded. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：解决的问题：提供一种可以通过改善半导体元件和覆盖它的密封树脂之间的粘附性或通过加强粘附不足的部分来保持耐热性的半导体器件。解决方案：半导体元件2具有通过表面上的接合线6连接的第一电极焊盘4。半导体元件2和接合线6被树脂密封。半导体元件2还具有与表面上的第一电极焊盘4A不同的第二电极焊盘4A。当半导体元件2组装在半导体器件中时，第二电极焊盘4A是不与外部电连接的。在第二电极焊盘4A上，接合凸块。版权所有（C）2006，JPO＆NCIPI

7. 发明专利

JP2002151644A LAMINATED SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF 失效
公开(公告)号：JP2002151644A
公开(公告)日：2002-05-24
申请号：JP2001121539
申请日：2001-04-19
申请人： FUJITSU LTD
发明人： KIKUMA KATSUTO , IKEDA MITSUTAKA , TSUKIDATE YOSHIHIRO , AKASHI YUJI , OZAWA KANAME , TAKASHIMA AKIRA , UNO TADASHI , NISHIMURA TAKAO , ANDO FUMIHIKO , ONODERA HIROSHI , OKUDA ISATO
IPC分类号： H01L23/12 , H01L23/31 , H01L25/065 , H01L25/07 , H01L25/18
摘要： PROBLEM TO BE SOLVED: To provide a laminated semiconductor device, which can house arbitrary sizes of a plurality of semiconductor elements in one package in a state that the elements are laminated, and to provide the manufacturing method of the laminated semiconductor device. SOLUTION: A laminated semiconductor device is constituted in a structure that a first semiconductor element 22 is mounted on a flexible printed board 26 provided with terminals for external connection. A printed circuit board 32 is provided on the element 22, and the element 22 is flip-chip mounted on the board 26. A second semiconductor element 24 is fixed on the board 32. The element 24 is wire-bonded to the board 26 and the element 22 is wire- bonded to the board 26 via the board 32.

8. 发明专利

JPH06129425A PRE-LOAD STRUCTURE OF BEARING AND MAGNETIC DISK DEVICE USING IT 失效
公开(公告)号：JPH06129425A
公开(公告)日：1994-05-10
申请号：JP28191992
申请日：1992-10-20
申请人： FUJITSU LTD
发明人： OGAWA YOSHINORI , NISHIMURA TAKAO
IPC分类号： F16C25/08 , G11B21/02
摘要： PURPOSE:To prevent the backlash of plural bearings by a simple pre-load means and realize high precision rotation and at the same time realize the reduction of work such as assembly and breaking-up. CONSTITUTION:In the case of bearing pre-load structure made up by being equipped with plural bearings 11 put between a rotary portion 7 and a fixed portion 10 and a pre-load means 15 to push-press respective bearings 11 radially against the rotary center axis of the bearings 11, the pre-load means 15 is composed of plural pushing portions to push plural bearings 11 respectively and an elastic means bent so as to retain and energize plural pushing portions.

9. 发明专利

JP2008047741A Circuit substrate and semiconductor device 有权
标题翻译：电路基板和半导体器件
公开(公告)号：JP2008047741A
公开(公告)日：2008-02-28
申请号：JP2006222825
申请日：2006-08-18
申请人： Fujitsu Ltd , 富士通株式会社
发明人： NISHIMURA TAKAO , AIBA KAZUYUKI
IPC分类号： H01L23/12
CPC分类号： H01L21/563 , H01L23/49838 , H01L24/29 , H01L24/32 , H01L24/75 , H01L24/83 , H01L24/90 , H01L2224/0401 , H01L2224/0558 , H01L2224/05624 , H01L2224/1134 , H01L2224/13144 , H01L2224/13147 , H01L2224/16225 , H01L2224/26175 , H01L2224/2919 , H01L2224/32057 , H01L2224/32225 , H01L2224/73203 , H01L2224/73204 , H01L2224/75743 , H01L2224/83096 , H01L2224/83192 , H01L2224/83194 , H01L2224/83385 , H01L2224/83855 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/0132 , H01L2924/014 , H01L2924/0665 , H01L2924/09701 , H01L2924/10329 , H01L2924/14 , H01L2924/15311 , H01L2924/19041 , H01L2924/19043 , H05K3/28 , H05K3/305 , H05K2201/09772 , H05K2201/09781 , H05K2201/09909 , H05K2201/10674 , H05K2201/10977 , Y02P70/613 , H01L2924/00 , H01L2924/01031 , H01L2924/00012 , H01L2924/3512
摘要： PROBLEM TO BE SOLVED: To provide a circuit substrate and a semiconductor device whose reliability and productivity are improved. SOLUTION: In a circuit substrate 100 to which the flip chip mounting of a semiconductor element 21 is carried out, at least one island-shaped conductive layer 14 is selectively arranged with a wiring layer 11a in an element mounting region on the circuit substrate 100, to which the semiconductor element 21 is fixed and an insulative resin layer 15 is arranged on the island-shaped conductive layer 14. The semiconductor element 21 is fixed in the element mounting region with an adhesive member 31 using the circuit substrate 100. Consequently, the lifting of a wiring layer or the damage to an electrode is suppressed in the inside of a semiconductor device 200, and the highly reliable circuit substrate 100 and the semiconductor device 200 using the circuit substrate 100 can be implemented. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：解决的问题：提供可靠性和生产率提高的电路基板和半导体装置。解决方案：在执行半导体元件21的倒装芯片安装的电路基板100中，至少一个岛状导电层14选择性地布置有电路中的元件安装区域中的布线层11a 衬底100，半导体元件21被固定到岛状导电层14上。绝缘树脂层15被布置在岛状导电层14上。半导体元件21使用电路衬底100用粘接构件31固定在元件安装区域中。因此，在半导体器件200的内部抑制布线层的提升或电极的损坏，可以实现使用电路基板100的高可靠性的电路基板100和半导体装置200。版权所有（C）2008，JPO＆INPIT

10. 发明专利

JP2007208210A Semiconductor device, and method for fabrication thereof 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2007208210A
公开(公告)日：2007-08-16
申请号：JP2006028860
申请日：2006-02-06
申请人： Fujitsu Ltd , 富士通株式会社
发明人： NISHIMURA TAKAO
IPC分类号： H01L21/60
CPC分类号： H01L21/563 , H01L23/3128 , H01L24/11 , H01L24/13 , H01L24/14 , H01L24/17 , H01L24/29 , H01L24/83 , H01L2224/05556 , H01L2224/05567 , H01L2224/05573 , H01L2224/05624 , H01L2224/05647 , H01L2224/11 , H01L2224/1134 , H01L2224/13 , H01L2224/13078 , H01L2224/1308 , H01L2224/13083 , H01L2224/13124 , H01L2224/13144 , H01L2224/13147 , H01L2224/1411 , H01L2224/16106 , H01L2224/16225 , H01L2224/16227 , H01L2224/32225 , H01L2224/73203 , H01L2224/73204 , H01L2224/83192 , H01L2224/85045 , H01L2924/00013 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01023 , H01L2924/01025 , H01L2924/01029 , H01L2924/01033 , H01L2924/01079 , H01L2924/01082 , H01L2924/0132 , H01L2924/014 , H01L2924/07802 , H01L2924/07811 , H01L2924/09701 , H01L2924/15311 , H01L2924/00014 , H01L2224/13099 , H01L2924/00 , H01L2924/00012 , H01L2924/3512
摘要： PROBLEM TO BE SOLVED: To provide a high performance, reliable semiconductor device which employs an adhesive to mount a semiconductor chip on a substrate (for example, flip chip mounting) and reduces air bubble generation within the adhesive, and to provide an inexpensive and efficient method for fabrication thereof. SOLUTION: This semiconductor device 10 comprises at least a semiconductor chip 11 for mounting multiple electrode pads 12 and a substrate 14 with multiple electrode terminals 15 corresponding to the positions of the electrode pads 12. The semiconductor chip 11 and the substrate 14 are adhered by an adhesive 17. A number of bumps 13, each consisting of a pedestal 13A and a projection 13B with a diameter smaller than that of the pedestal 13A, are formed on at least one of the electrode pads 12, in a way that the pedestals 13A in the respective bumps 13 contact and the bumps 13 and electrode terminals 15 are electrically connected. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：为了提供使用粘合剂将半导体芯片安装在基板上的高性能，可靠的半导体器件（例如，倒装芯片安装）并且减少粘合剂内的气泡产生，并且提供一种廉价和有效的制造方法。解决方案：该半导体器件10至少包括用于安装多个电极焊盘12的半导体芯片11和具有对应于电极焊盘12的位置的多个电极端子15的衬底14.半导体芯片11和衬底14是通过粘合剂17粘合。在至少一个电极焊盘12上形成有多个由基座13A和直径小于基座13A直径的突起13B组成的凸块13，各个凸块13中的基座13A接触，凸块13和电极端子15电连接。版权所有（C）2007，JPO＆INPIT

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