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1. 发明专利

JP2004103181A Semiconductor nonvolatile memory which has improved tracking characteristic 审中-公开
公开(公告)号：JP2004103181A
公开(公告)日：2004-04-02
申请号：JP2002267097
申请日：2002-09-12
申请人： Fujitsu Ltd , 富士通株式会社
发明人： TAKAHASHI SATOSHI , KURIHARA KAZUHIRO
IPC分类号： G11C16/04 , G11C16/02 , G11C16/06
摘要： PROBLEM TO BE SOLVED: To provide a nonvolatile memory obtained by tracking the threshold voltage characteristic of reference-side cell transistors to the characteristic of a core-side cell transistor. SOLUTION: The nonvolatile memory in which data is stored depending of a difference in threshold voltage has the core-side cell transistor C-MC to which an electric charge is injected depending on stored data and the reference-side cell transistors RA-MC and RB-MC supplying a reference level when reading data from the core-side cell transistor. In the program operation of injecting electric charges depending on the stored data, the core-side cell transistor is impressed with first drain voltage and the reference-side cell transistors are impressed with second a drain voltage lower than the first drain voltage. COPYRIGHT: (C)2004,JPO

2. 发明专利

JP2004039234A System for utilizing dynamic reference by two-bit cell memory 有权
公开(公告)号：JP2004039234A
公开(公告)日：2004-02-05
申请号：JP2003274071
申请日：2003-07-14
申请人： Fujitsu Ltd , 富士通株式会社
发明人： KURIHARA KAZUHIRO
IPC分类号： H01L21/66 , G11C11/56 , G11C16/02 , G11C16/04 , G11C16/06 , G11C16/28
CPC分类号： G11C11/5621 , G11C11/5642 , G11C16/28 , G11C2211/5634
摘要： PROBLEM TO BE SOLVED: To provide a system for utilizing dynamic reference by a two-bit cell memory. SOLUTION: This invention provides a method of reading and identifying a two-bit core cell in a memory device. A memory device has a dynamic reference cell and a fixed reference cell. The method comprises a step of programming the dynamic reference cell using the fixed reference cell, and a step of programming the two-bit core cell using the dynamic reference cell. When the dynamic reference cell is provided on the same word line with a core cell, the constant current source applied to a core cell data line operates during program verification, so that the difference of current is provided between the core cell and the dynamic reference cell. COPYRIGHT: (C)2004,JPO

3. 发明专利

JP2003068090A Semiconductor memory and source side detecting circuit 审中-公开
标题翻译：半导体存储器和源极检测电路
公开(公告)号：JP2003068090A
公开(公告)日：2003-03-07
申请号：JP2002214179
申请日：2002-07-23
申请人： Fujitsu Ltd , 富士通株式会社
发明人： KURIHARA KAZUHIRO
IPC分类号： G11C16/06 , G11C7/06 , G11C16/28
CPC分类号： G11C7/062 , G11C7/067 , G11C16/28 , G11C2207/063
摘要： PROBLEM TO BE SOLVED: To provide a system detecting presence of a cell current in a source side in a memory device. SOLUTION: This system comprises a source side detecting circuit used in a memory device for discriminating core cell data from a core cell current. The source side detecting circuit is provided with a constant current source connected for obtaining a core cell current, and a cascade circuit connected to the constant current source and converting a core cell current to output voltage indicating core cell data.
摘要翻译：要解决的问题：提供一种检测存储器件中的源侧的单元电流的存在的系统。解决方案：该系统包括在存储器装置中使用的源侧检测电路，用于从核心单元电流鉴别核心单元数据。源侧检测电路具有连接用于获得核心单元电流的恒流源，连接到恒流源的级联电路，并将核心单元电流转换成指示核心单元数据的输出电压。

4. 发明专利

JP2004297922A Charging pump circuit 有权
标题翻译：充电泵电路
公开(公告)号：JP2004297922A
公开(公告)日：2004-10-21
申请号：JP2003087868
申请日：2003-03-27
申请人： Fujitsu Ltd , 富士通株式会社
发明人： KURIHARA KAZUHIRO
IPC分类号： G11C16/06 , H02M3/07 , H03K19/096
摘要： PROBLEM TO BE SOLVED: To provide a charge pump circuit capable of reducing power consumption. SOLUTION: A first clock generating circuit generates a plurality of first clocks, having the same phase as each other. A charge pump has a plurality of first capacitance elements, of which one end receives each of the first clocks and of which the other end is connected with a first node to generate a first boosting voltage at an output node utilizing charging and discharging of the first capacitance elements. The first clock-generating circuit has a plurality of first clock output circuits at the first clock so that they correspond to each other. Each of the first clock output circuits outputs each of the first clocks at a first driving ability, when the first boosting voltage is lower than a target voltage, and at a second driving ability lower than the first driving ability, when the first boosting voltage is higher than the target voltage. COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：提供能够降低功耗的电荷泵电路。解决方案：第一时钟发生电路产生具有彼此相同相位的多个第一时钟。电荷泵具有多个第一电容元件，其一端接收每个第一时钟，并且另一端与第一节点连接，以在输出节点处产生第一升压电压，利用第一时钟的充电和放电电容元件。第一时钟发生电路在第一时钟具有多个第一时钟输出电路，使得它们彼此对应。第一时钟输出电路中的每一个以第一驱动能力输出第一时钟，当第一升压电压低于目标电压时，以及比第一驱动能力低的第二驱动能力，当第一升压电压为高于目标电压。版权所有（C）2005，JPO＆NCIPI

5. 发明专利

JP2003068091A System and method for boosting word line signal of memory device 有权
标题翻译：用于提升存储器设备的字线信号的系统和方法
公开(公告)号：JP2003068091A
公开(公告)日：2003-03-07
申请号：JP2002178882
申请日：2002-06-19
申请人： Fujitsu Ltd , 富士通株式会社
发明人： KURIHARA KAZUHIRO
IPC分类号： G11C16/06 , G11C8/08 , G11C16/08 , H02M3/07
CPC分类号： G11C8/08 , G11C16/08
摘要： PROBLEM TO BE SOLVED: To provide a system for boosting a signal used for a memory device without depending on supply voltage. SOLUTION: As one example of a system, a boost-signal generating circuit for generating a boost-signal used for producing a word line signal in a memory device comprises a pre-charge circuit and a boosting circuit. The pre-charge circuit has an input terminal for receiving an address signal and a boost-control signal, and an output terminal for outputting a pre-charge signal previously set to the prescribed initial voltage. The boosting circuit receives a boost-control signal and outputs a boost-activation signal in accordance with an address control signal. The boost-drive signal is coupled to an output signal of the pre-charge circuit through a capacitive element. When a boost-drive signal is active, a pre-charge signal is raised to the prescribed boost-level which is independent of supply voltage.
摘要翻译：要解决的问题：提供用于升高用于存储器件的信号而不依赖于电源电压的系统。解决方案：作为系统的一个例子，用于产生用于在存储器件中产生字线信号的升压信号的升压信号产生电路包括预充电电路和升压电路。预充电电路具有用于接收地址信号和升压控制信号的输入端子和用于输出预先设定为规定的初始电压的预充电信号的输出端子。升压电路接收升压控制信号，并根据地址控制信号输出升压启动信号。升压驱动信号通过电容元件耦合到预充电电路的输出信号。当升压驱动信号有效时，预充电信号升高到与电源电压无关的规定升压电平。

6. 发明专利

JP2003068087A Method and device for reading dual bit memory cell 有权
标题翻译：用于读取双位存储单元的方法和设备
公开(公告)号：JP2003068087A
公开(公告)日：2003-03-07
申请号：JP2002177482
申请日：2002-06-18
申请人： Fujitsu Ltd , 富士通株式会社
发明人： KURIHARA KAZUHIRO
IPC分类号： G11C16/02 , G11C16/04 , G11C16/06 , G11C16/28 , H01L21/8247 , H01L27/10 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： G11C16/0475 , G11C16/28
摘要： PROBLEM TO BE SOLVED: To provide a method for reading dual bit memory cells and a y- decoder system configured for reading two sides by using a multi-reference cell by reading two sides especially in reading of dual bit memory cells. SOLUTION: In the method for reading a programmed dual bit memory cell selected by using a plurality of programmed dual bit reference cells, the reference cell is programmed corresponding to a plurality of programming parameters to select a programming parameter for compensating the aging characteristics of the selected programmed dual bit memory cell and on the basis of the first and second data bits of a plurality of programmed reference cells, the first and second data bits of the selected programmed memory cell are determined.
摘要翻译：要解决的问题：提供一种用于读取双位存储单元的方法和配置用于通过读取双面特别是读取双位存储单元而使用多参考单元来读取双面的y解码器系统。解决方案：在用于读取通过使用多个编程的双位参考单元选择的编程双位存储器单元的方法中，参考单元被编程为对应于多个编程参数，以选择用于补偿所选择的老化特性的编程参数编程的双位存储单元，并且基于多个编程的参考单元的第一和第二数据位，确定所选择的编程存储器单元的第一和第二数据位。

7. 发明专利

JP2004248475A Charge pump circuit with reduced amplitude of step-up voltage 有权
公开(公告)号：JP2004248475A
公开(公告)日：2004-09-02
申请号：JP2003038642
申请日：2003-02-17
申请人： Fujitsu Ltd , 富士通株式会社
发明人： KURIHARA KAZUHIRO
IPC分类号： H01L27/04 , H01L21/822 , H02M3/07
摘要： PROBLEM TO BE SOLVED: To provide a charge pump circuit, low in power consumption. SOLUTION: The charge pump circuit which increases supply voltage comprises a plurality of charge pump units Pump 0 to 3, and a control circuit 200 which controls the number of activated charge pump units. When the charge pump voltage generated by the charge pump units changes so that it will fall below a first target voltage, the control circuit increases the number of activated charge pump units. When the charge pump voltage changes so that it will exceed a second target voltage lower than the first target voltage, the control circuit decreases the number of activated charge pump units. Thus, the control of the control circuit which controls the activated state of a plurality of charge pump units is provided with hysteresis characteristics. Therefore, the amplitude of the generated charge pump voltage can be suppressed. Consequently, the level of the generated charge pump voltage can be made close to a minimum required level. As a result, excessive step-up operation can be avoided, and the power consumption can be reduced. COPYRIGHT: (C)2004,JPO&NCIPI

8. 发明专利

JP2004247689A Step-up circuit of small area with multistage structure 有权
公开(公告)号：JP2004247689A
公开(公告)日：2004-09-02
申请号：JP2003038636
申请日：2003-02-17
申请人： Fujitsu Ltd , 富士通株式会社
发明人： KURIHARA KAZUHIRO
IPC分类号： H01L27/04 , H01L21/822
摘要： PROBLEM TO BE SOLVED: To obtain a step-up circuit of a small area by lowering the withstand voltage of a capacitor for boosting.
SOLUTION: In a step-up circuit with a multistage structure responding to a clock to boost an output node, there are provided at least a first-stage boosting unit 100 and a second-stage boosting unit 200 in which the output of the first-stage boosting unit is inputted. The first and second stage boosting units have an input terminal supplied with predetermined voltage, an output terminal connected with the input terminal by a switch SW, and a boosting capacitor C with one electrode connected with the output terminal and the other electrode supplied with the boosting clocks A and B1, respectively. When the switch conducts, the voltage of the input terminal is transmitted to the output terminal. Responding to a clock applied after that, the output terminal is boosted. The potential of the clock of the second-stage boosting unit is higher than that of the clock of the first-stage boosting unit.
COPYRIGHT: (C)2004,JPO&NCIPI

9. 发明专利

JP2004110881A Semiconductor memory 有权
标题翻译：半导体存储器
公开(公告)号：JP2004110881A
公开(公告)日：2004-04-08
申请号：JP2002268606
申请日：2002-09-13
申请人： Fujitsu Ltd , 富士通株式会社
发明人： NAKAI TSUTOMU , YAMASHITA MINORU , ANDY CHEN , KURIHARA KAZUHIRO
IPC分类号： G11C16/06 , G11C16/04
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor memory capable of correctly reading data in a core cell with a large margin. SOLUTION: The semiconductor memory is provided with the core cell 11, at least one internal reference cell 12, 13 arranged within the area of core cell, at least one external reference cell 50 arranged outside the core cell, and a reference voltage generation circuit 40 for generating the reference voltage Vref by using at least one of the internal reference cells and at least one external reference cell jointly at the same time. The reference voltage generation circuit is provided with switch circuits 41, 42 for controlling the connections between the internal reference cells and the external reference cells and a control circuit 43 for controlling the switch circuits, and is configured so as to read the data stored in the core cell by using the output of the reference voltage generation circuit. COPYRIGHT: (C)2004,JPO
摘要翻译：要解决的问题：提供能够以大幅度正确读取核心单元中的数据的半导体存储器。解决方案：半导体存储器设置有核心单元11，布置在核心单元的区域内的至少一个内部参考单元12,13，布置在核心单元外部的至少一个外部参考单元50以及参考电压生成电路40，用于通过同时使用内部参考单元和至少一个外部参考单元中的至少一个来产生参考电压Vref。参考电压产生电路设置有用于控制内部参考单元和外部参考单元之间的连接的开关电路41,42和用于控制开关电路的控制电路43，并且被配置为读取存储在使用参考电压产生电路的输出。版权所有（C）2004，JPO

10. 发明专利

JP2004103143A Memory circuit having redundancy constitution 审中-公开
公开(公告)号：JP2004103143A
公开(公告)日：2004-04-02
申请号：JP2002265065
申请日：2002-09-11
申请人： Fujitsu Ltd , 富士通株式会社
发明人： TSUKIDATE YOSHIHIRO , KURIHARA KAZUHIRO , RYU SEI , NAKAI TSUTOMU , ANDY CHEN
IPC分类号： G11C16/06 , G11C16/02 , G11C29/00 , G11C29/04 , G11C29/24
CPC分类号： G11C29/82 , G11C29/24 , G11C29/846
摘要： PROBLEM TO BE SOLVED: To provide a memory circuit with redundancy constitution in which a reduction in access speed caused by redundancy discrimination is suppressed. SOLUTION: In a memory circuit having a plurality of blocks having a plurality of regular sectors and spare sectors, each sector has a plurality of memory cells, when a regular sector in a first block is defective, the defective regular sector is replaced by a spare sector in a second block. And a spare sector in the second block is selected simultaneously with a regular sector corresponding to a selection address in the first block during a first period responding to a supplied address, after the first period, the selection of either of a regular sector or a spare sector is kept in accordance with a redundancy discrimination result of whether the supplied address coincides with a redundancy address or not. COPYRIGHT: (C)2004,JPO

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