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1. 发明专利

JP2004221459A Semiconductor device and its manufacturing method 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2004221459A
公开(公告)日：2004-08-05
申请号：JP2003009490
申请日：2003-01-17
申请人： Elpida Memory Inc , Hitachi Ltd , Hitachi Ulsi Systems Co Ltd , エルピーダメモリ株式会社 , 株式会社日立製作所 , 株式会社日立超エル・エス・アイ・システムズ
发明人： KITAMURA EIJI , YAMADA SATORU , KATO YOSHIKI , SAINO KANTA , SAITO MASAYOSHI , IIJIMA SHINPEI , OYU SHIZUNORI
IPC分类号： H01L21/28 , H01L21/8238 , H01L27/092 , H01L29/423 , H01L29/49 , H01L29/78
CPC分类号： H01L21/28247
摘要： PROBLEM TO BE SOLVED: To reduce the gate resistance of a semiconductor device by reducing contact resistance between a tungsten film and a polysilicon layer, and at the same time, suppressing the occurrence of depletion in the gate electrode of the device.
SOLUTION: At the time of manufacturing the semiconductor device in which the gate electrode is constituted in a three-layered poly-metal gate structure composed of the tungsten film (W) 23, a tungsten nitride film (WN) 24, and the polysilicon layer (PolySi) 22; the side face of the gate electrode is nitrided at a nitriding temperature of 700-950°C in an ammonia atmosphere before the side face is selectively oxidized after the gate electrode is formed.
COPYRIGHT: (C)2004,JPO&NCIPI
摘要翻译：要解决的问题：通过降低钨膜和多晶硅层之间的接触电阻，同时抑制器件的栅极电极的耗尽，从而降低半导体器件的栅极电阻。解决方案：在制造其中栅电极由钨膜（W）23，氮化钨膜（WN）24和氮化钨膜（W））组成的三层多金属栅极结构中的半导体器件制造时，多晶硅层（PolySi）22; 在形成栅极电极之后，在侧面被选择性地氧化之前，在氨气氛中，在700-950℃的氮化温度下氮化栅电极的侧面。版权所有（C）2004，JPO＆NCIPI

2. 发明专利

JP2006252648A Dynamic random access memory device and test method therefor 有权
标题翻译：动态随机存取存储器及其测试方法
公开(公告)号：JP2006252648A
公开(公告)日：2006-09-21
申请号：JP2005066657
申请日：2005-03-10
申请人： Elpida Memory Inc , Hitachi Ltd , エルピーダメモリ株式会社 , 株式会社日立製作所
发明人： MORI TOMONORI , YAMADA RENICHI , TSUKADA SHUICHI , OYU SHIZUNORI
IPC分类号： G11C29/56 , G01R31/28 , G01R31/30 , G11C11/401 , G11C29/44
CPC分类号： G11C29/50 , G11C11/401 , G11C29/50016
摘要： PROBLEM TO BE SOLVED: To screen a so-called variable retention time (VRT) defect caused by the fact that a data retention time varies like random telegraph noise in DRAM. SOLUTION: A bit which may cause a retention defect of a data retention capability resulting from random changes with time is screened by repeating a pause refresh test for checking a data retention function in the whole chip surface and the whole bits by an optimized frequency. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：为了屏蔽由DRAM中的随机电报噪声等数据保持时间变化所引起的所谓可变保留时间（VRT）缺陷。解决方案：通过重复暂停刷新测试来检查可能导致随时间随机变化产生的数据保留能力的一个位，以便通过优化的整个芯片表面和整个比特来检查数据保留功能频率。版权所有（C）2006，JPO＆NCIPI

3. 发明专利

JP2006040991A Method of evaluating semiconductor device and manufacturing method thereof 审中-公开
标题翻译：评估半导体器件的方法及其制造方法
公开(公告)号：JP2006040991A
公开(公告)日：2006-02-09
申请号：JP2004215183
申请日：2004-07-23
申请人： Elpida Memory Inc , Hitachi Ltd , エルピーダメモリ株式会社 , 株式会社日立製作所
发明人： TAKATO ATSUKO , NOZOE MARI , OYU SHIZUNORI
IPC分类号： H01L21/66 , H01L21/8238 , H01L21/8242 , H01L27/092 , H01L27/108
CPC分类号： H01L22/14 , G01R31/2653 , H01L2924/0002 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a technology which makes it possible to evaluate the leak characteristics distribution in a pn junction in the middle of manufacturing process of a semiconductor device having the pn junction, and to rapidly feed back the evaluation results to decision making of manufacturing process conditions. SOLUTION: For a wafer in the middle of manufacturing process, an electron beam is irradiated several times on the surface of the wafer whereon a plug is exposed at prescribed intervals under such a condition that the pn junction may be reverse-biased. Monitoring the charged potential of the surface of the plug, the electron beam irradiation conditions are changed to such ones that the charged potential may come within a desired range. Under such irradiation conditions, a secondary electron signal of a circuit pattern is obtained and the leak characteristics are evaluated. Since the charged potential in the pn junction is relaxed according to the size of the leakage current within intermittent time, the leak characteristics are evaluated from the brightness signal of a potential contrast image. Thus, by measuring the charged potential and making it within a desired range, the evaluation results reflect a state in actual operation and thereby the accuracy improves. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供一种能够在具有pn结的半导体器件的制造过程中评估pn结中的泄漏特性分布的技术，并且将评估结果快速反馈到制造工艺条件的决策。解决方案：对于在制造过程中间的晶片，在pn结可以被反向偏置的条件下，以规定的间隔将电子束照射在晶片的表面上，在该表面上暴露一个电极。监测插头表面的带电电位，将电子束照射条件改变为充电电位可能在期望范围内的条件。在这种照射条件下，获得电路图案的二次电子信号，并评价泄漏特性。由于根据间歇时间内的漏电流的大小使pn结中的充电电位松弛，所以根据潜在对比度图像的亮度信号来评价泄漏特性。因此，通过测量充电电位并使其在期望的范围内，评价结果反映实际操作中的状态，从而提高精度。版权所有（C）2006，JPO＆NCIPI

4. 发明专利

JP2007150129A Semiconductor chip having island-shaped scattering structure and manufacturing method therefor 有权
标题翻译：具有岛屿形状散射结构的半导体芯片及其制造方法
公开(公告)号：JP2007150129A
公开(公告)日：2007-06-14
申请号：JP2005345056
申请日：2005-11-30
申请人： Elpida Memory Inc , Hitachi Ltd , エルピーダメモリ株式会社 , 株式会社日立製作所
发明人： OYU SHIZUNORI , AOKI SHIGERU
IPC分类号： H01L21/02
CPC分类号： H01L23/562 , H01L21/306 , H01L21/30604 , H01L21/3065 , H01L21/308 , H01L21/78 , H01L23/26 , H01L23/3128 , H01L29/0657 , H01L2924/0002 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a highly reliable semiconductor chip that scarcely gets damaged. SOLUTION: The semiconductor chip includes a semiconductor silicon substrate having a semiconductor element layer and porous silicon domain layer, wherein the silicon element layer is prepared on a front principal surface region which is one surface of the semiconductor silicon substrate, while the porous silicon domain layer is prepared on a back principal surface which is the other surface of the semiconductor silicon substrate, and the porous silicon domains in the porous silicon domain layer are scattered in an island shape on the back surface of the semiconductor silicon substrate. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供几乎不会损坏的高度可靠的半导体芯片。解决方案：半导体芯片包括具有半导体元件层和多孔硅畴层的半导体硅衬底，其中硅元素层制备在作为半导体硅衬底的一个表面的前主表面区域上，而多孔在作为半导体硅衬底的另一个表面的背面主表面上制备硅域层，并且多孔硅畴层中的多孔硅区域以岛状分散在半导体硅衬底的背面上。版权所有（C）2007，JPO＆INPIT

5. 发明专利

JP2004063527A Semiconductor memory device and its manufacturing method 审中-公开
公开(公告)号：JP2004063527A
公开(公告)日：2004-02-26
申请号：JP2002216112
申请日：2002-07-25
申请人： Elpida Memory Inc , Hitachi Ltd , Hitachi Ulsi Systems Co Ltd , エルピーダメモリ株式会社 , 株式会社日立製作所 , 株式会社日立超エル・エス・アイ・システムズ
发明人： OYU SHIZUNORI , OGISHIMA JUNJI , UCHIYAMA HIROYUKI , KAWAKITA KEIZO , SUZUKI MASATO
IPC分类号： H01L21/76 , H01L21/265 , H01L21/336 , H01L21/762 , H01L21/8234 , H01L21/8242 , H01L27/108
CPC分类号： H01L21/76237 , H01L21/26586 , H01L21/823481 , H01L27/10873
摘要： PROBLEM TO BE SOLVED: To prevent the refreshing characteristics deteriorated by the influence of adjacent word lines of adjacent cells and to enable to reduce defects a after packaging and reflowing. SOLUTION: An active region 1 has a diffused layer in a region sandwiched between word lines 4, 2, 3 and 5. The diffused layer 6 sandwiched between the word lines 2 and 3 is connected to a bit line via a contact, and a diffused layer 7 sandwiched between the word lines 2 and 4 and a diffused layer 8 sandwiched between the word lines 3 and 5 are connected to respective capacities through a contact. A cell structure has two cell transistors in which the word line 2 is used as a gate electrode, and the diffused layers 6, 7 are used as source/drain. In the structure, the word line 3 is used as a gate electrode, and the diffused layers 6, 8 are used as source/drain. N-type diffused layers 7, 8 formed of the word lines 2, 3 adjacent to the word lines 4, 5 have a high n-type carrier concentration at the word lines 4, 5 sides from the word lines 2, 3 sides, or a p-type substrate concentration is set to a low concentration at the word lines 4, 5 sides. COPYRIGHT: (C)2004,JPO

6. 发明专利

JP2009176808A Method of manufacturing semiconductor device 审中-公开
标题翻译：制造半导体器件的方法
公开(公告)号：JP2009176808A
公开(公告)日：2009-08-06
申请号：JP2008011387
申请日：2008-01-22
申请人： Elpida Memory Inc , Hitachi Ltd , エルピーダメモリ株式会社 , 株式会社日立製作所
发明人： OYU SHIZUNORI , OKONOGI KENSUKE , SHIMA AKIO
IPC分类号： H01L21/265 , H01L29/78
CPC分类号： H01L21/26506 , H01L21/26513 , H01L21/268 , H01L29/1083 , H01L29/78
摘要： PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor device which is not limited by the concentration of a diffusion layer and of which junction leak current is reduced enough.
SOLUTION: The method of manufacturing a semiconductor device includes: a step to dope an area of first conductivity type of a silicon substrate with impurities of second conductivity type opposite to first conductivity type and heat it so as to form a diffusion layer of the second conductivity type; and a step to implant nitride or fluorine ions to the diffusion layer and give a carbon dioxide gas laser to the diffusion layer.
COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：解决的问题：提供一种半导体器件的制造方法，其不受扩散层的浓度的限制，并且结合漏电流足够减少。解决方案：半导体器件的制造方法包括：将具有与第一导电类型相反的第二导电类型的杂质的第一导电类型的硅衬底的区域掺杂并加热的步骤，以形成扩散层第二导电类型; 以及将氮化物或氟离子注入扩散层并向扩散层产生二氧化碳气体激光的步骤。版权所有（C）2009，JPO＆INPIT

7. 发明专利

JP2004087757A Semiconductor device and its manufacturing method 有权
公开(公告)号：JP2004087757A
公开(公告)日：2004-03-18
申请号：JP2002246287
申请日：2002-08-27
申请人： Elpida Memory Inc , Hitachi Ltd , エルピーダメモリ株式会社 , 株式会社日立製作所
发明人： YAMADA SATORU , NAGAI AKIRA , OYU SHIZUNORI , NAKAMURA RYOICHI , TAKAURA NORIKATSU
IPC分类号： H01L27/092 , H01L21/28 , H01L21/8238 , H01L21/8242 , H01L27/108 , H01L29/49 , H01L29/78
CPC分类号： H01L27/10891 , H01L21/28061 , H01L21/823842 , H01L27/10894 , H01L27/10897 , H01L29/4941 , H01L29/7833
摘要： PROBLEM TO BE SOLVED: To provide a transistor, special to a DRAM (dynamic random access memory) for simultaneously achieving three points of improvement of the performance of a PMOS (p-channel metal oxide semiconductor) in the circumferential circuit of the DRAM, the reduction of a word line resistance and the mitigation of junction field of a memory cell.
SOLUTION: In the semiconductor device of a gate electrode structure consisting of three levels or more of Fermi level polysilicon, P-type polysilicon having the lowest Fermi level is arranged in a first N-type surface channel MOS (metal-oxide-semiconductor) transistor 13, N-type polysilicon having the highest Fermi level, is arranged in a second N-type surface channel MOS transistor 12 and the N-type polysilicon, having an intermediate Fermi level and produced through doping both of N-type impurities and P-type impurities, is arranged in a P-channel MOS transistor 11 respectively.
COPYRIGHT: (C)2004,JPO

8. 发明专利

JP2009117653A Semiconductor device, and method of manufacturing the same 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2009117653A
公开(公告)日：2009-05-28
申请号：JP2007289784
申请日：2007-11-07
申请人： Elpida Memory Inc , Hitachi Ltd , エルピーダメモリ株式会社 , 株式会社日立製作所
发明人： OYU SHIZUNORI , HOZAWA KAZUYUKI
IPC分类号： H01L21/304 , B24B1/00 , H01L21/301
CPC分类号： B24B37/042 , H01L21/02057 , H01L21/304 , H01L2924/0002 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device having such a Cu distribution that the semiconductor element, and the like, of a transistor, and the like, existing on the front surface side of its semiconductor substrate will not be subjected to Cu pollution, when it is packaged, and which has superior yield, and to provide a method of manufacturing the device. SOLUTION: (1) In the method of manufacturing the semiconductor device, coarse and finishing grindings of its incomplete product are performed from the opposite rear-surface side of its silicon semiconductor substrate and its side provided with a semiconductor element, by using a grinding stone whose copper content is smaller than 1 ppm. (2) Furthermore, in the manufacturing method, the cleaning of the rear-surface side of its silicon semiconductor substrate is performed by silicon chemical etching, and the content of copper locally in the portion whose boundaries are separated by 3 nm from the rear-surface side of its silicon semiconductor substrate is set to be not larger than 1×10 9 /cm 2 . COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：为了提供具有这样的Cu分布的半导体器件，半导体衬底的表面侧上存在的晶体管等的半导体元件等将不会受到 Cu污染，包装时，具有优异的产率，并提供制造该装置的方法。（1）在半导体装置的制造方法中，从其硅半导体基板的相对的背面侧及其配置有半导体元件的一侧，通过使用半导体元件的粗糙和精加工研磨，铜含量小于1ppm的研磨石。（2）此外，在制造方法中，通过硅化学蚀刻来进行硅半导体基板的背面侧的清洗，在边界与背面侧分离3nm的部分局部存在铜的含量，其硅半导体衬底的表面侧被设定为不大于1×10 / cm 2 。版权所有（C）2009，JPO＆INPIT

9. 发明专利

JP2006150500A Resin bonded abrasive wheel and semiconductor chip manufacturing method using the same 审中-公开
标题翻译：树脂粘合磨轮和半导体芯片制造方法
公开(公告)号：JP2006150500A
公开(公告)日：2006-06-15
申请号：JP2004344628
申请日：2004-11-29
申请人： Akita Denshi Systems:Kk , Akita Semiconductor:Kk , Elpida Memory Inc , Hitachi Ltd , エルピーダメモリ株式会社 , 株式会社アキタセミコンダクタ , 株式会社アキタ電子システムズ , 株式会社日立製作所
发明人： OYU SHIZUNORI , HOZAWA KAZUYUKI , SAKURADA SHINICHI
IPC分类号： B24D3/00 , C09J11/04 , C09J201/00 , H01L21/301 , H01L21/304
CPC分类号： B24D3/28 , B24B37/042
摘要： PROBLEM TO BE SOLVED: To provide a resin bonded abrasive wheel capable of giving a highly reliable semiconductor device even when the thickness of a semiconductor chip is reduced, and a semiconductor chip manufacturing method using the same. SOLUTION: [1] The resin bonded abrasive wheel is provided with abrasive grains, which are coated by cobalt, iron, manganese, chromium, vanadium, and at least one kind of magnetic metal selected from a group composed of an alloy made of the above metals, and a resin. The abrasive grains coated by the magnetic metal are dispersed in the resin. [2] The semiconductor chip manufacturing method includes a process for grinding a semiconductor wafer by using the resin bonded abrasive wheel and a process for dicing the semiconductor wafer after the grinding. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：即使当半导体芯片的厚度减小时，也可提供能够提供高度可靠的半导体器件的树脂粘合砂轮，以及使用该树脂粘合砂轮的半导体芯片制造方法。 [1]解决方案：[1]树脂粘合砂轮设置有磨粒，其被钴，铁，锰，铬，钒和至少一种选自由合金制成的组中的至少一种磁性金属的上述金属和树脂。被磁性金属涂覆的磨粒分散在树脂中。半导体芯片制造方法包括通过使用树脂粘合砂轮研磨半导体晶片的方法和在研磨之后切割半导体晶片的工艺。版权所有（C）2006，JPO＆NCIPI

10. 发明专利

JP2011181729A Method of manufacturing semiconductor device 审中-公开
标题翻译：制造半导体器件的方法
公开(公告)号：JP2011181729A
公开(公告)日：2011-09-15
申请号：JP2010045188
申请日：2010-03-02
申请人： Elpida Memory Inc , エルピーダメモリ株式会社
发明人： MUNETAKA YUKI , OYU SHIZUNORI
IPC分类号： H01L23/522 , H01L21/768 , H01L21/8242 , H01L27/108
摘要： PROBLEM TO BE SOLVED: To effectively prevent a short-circuiting between a wiring line and a contact plug.
SOLUTION: In a method of manufacturing a semiconductor device, a plurality of contact holes including a first contact hole where a wiring line is exposed are formed in an inter-layer insulating film positioned between adjacent wiring lines. Then a part of the exposed wiring is removed so that: (i) a side face where the wiring line is exposed is substantially flush with an inner wall side face comprised of a first insulating film of the first contact hole; or (ii) the side face where the wiring line is exposed is formed into a hollowed recess shape in the inner wall side face of the first contact hole. Then a side wall film is formed on the inner wall side face of the contact hole, and then the contact hole is filled with a conductive material to form the contact plug.
COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：有效地防止布线和接触插头之间的短路。解决方案：在制造半导体器件的方法中，在位于相邻布线之间的层间绝缘膜中形成包括布线布线的第一接触孔的多个接触孔。然后，暴露的布线的一部分被去除，使得：（i）布线被暴露的侧面与由第一接触孔的第一绝缘膜构成的内壁侧面基本齐平; 或者，（ii）在第一接触孔的内壁侧面形成有露出线的侧面形成中空的凹部形状。然后在接触孔的内壁侧面上形成侧壁膜，然后用导电材料填充接触孔以形成接触塞。版权所有（C）2011，JPO＆INPIT

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