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1. 发明专利

JP2011249396A Method of manufacturing semiconductor device 审中-公开
标题翻译：制造半导体器件的方法
公开(公告)号：JP2011249396A
公开(公告)日：2011-12-08
申请号：JP2010118294
申请日：2010-05-24
申请人： Elpida Memory Inc , エルピーダメモリ株式会社
发明人： MUNETAKA YUKI , HIROTA TOSHIYUKI , UEDA YASUHIKO
IPC分类号： H01L21/8242 , H01L21/336 , H01L27/108 , H01L29/78
摘要： PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor device without needing to form a mask pattern covering only a part of a trench, by using a photoresist film.SOLUTION: A method of manufacturing a semiconductor device comprises the steps of: forming a first trench 7 in a semiconductor substrate 1; forming a first insulator film 8 in the first trench 7; filling the first trench 7 with a first conductive film 9 so that a top surface of the first conductive film 9 is below a top edge of the first insulator film; forming a carbon film 10 on a side surface of the first trench 7; filling the first trench 7 with a second insulator film 11; removing the carbon film 10 that covers one side surface of the first trench 7 to expose a part of the first insulator film 8; and removing the second insulator film 11 and the exposed first insulator film 8 to expose a part of the semiconductor substrate 1.
摘要翻译：要解决的问题：提供一种制造半导体器件的方法，而不需要通过使用光致抗蚀剂膜形成仅覆盖沟槽的一部分的掩模图案。解决方案：制造半导体器件的方法包括以下步骤：在半导体衬底1中形成第一沟槽7; 在第一沟槽7中形成第一绝缘膜8; 用第一导电膜9填充第一沟槽7，使得第一导电膜9的顶表面在第一绝缘膜的顶边下方; 在第一沟槽7的侧表面上形成碳膜10; 用第二绝缘膜11填充第一沟槽7; 去除覆盖第一沟槽7的一个侧表面的碳膜10以暴露第一绝缘膜8的一部分; 并且去除第二绝缘膜11和暴露的第一绝缘膜8以暴露半导体衬底1的一部分。版权所有：（C）2012，JPO＆INPIT

2. 发明专利

JP2012089772A Method of manufacturing semiconductor device 审中-公开
标题翻译：制造半导体器件的方法
公开(公告)号：JP2012089772A
公开(公告)日：2012-05-10
申请号：JP2010237012
申请日：2010-10-22
申请人： Elpida Memory Inc , エルピーダメモリ株式会社
发明人： MUNETAKA YUKI , TAKAISHI YOSHIHIRO
IPC分类号： H01L21/8242 , H01L21/336 , H01L27/108 , H01L29/41 , H01L29/78
CPC分类号： H01L29/7827 , H01L29/42356 , H01L29/4238 , H01L29/66666
摘要： PROBLEM TO BE SOLVED: To reduce the probability of breaking of a gate electrode.SOLUTION: A method of manufacturing a semiconductor device 1 comprises the steps of: forming an insulating pillar 6 on a primary surface of a silicon substrate 2; forming a protective film 12 on the side surface of the insulating pillar 6; forming a silicon pillar 4 on the primary surface of the silicon substrate 2; forming a gate insulating film 10 on the side surface of the silicon pillar 4; and forming a first and second gate electrodes 11 and 13 that cover the side surfaces of the silicon pillar 4 and the insulating pillar 6, respectively, and contact mutually. According to the manufacturing method, since the protective film 12 is formed on the side surface of the insulating pillar 6 that is a dummy pillar, chipping of the dummy pillar is prevented in processing the silicon pillar 4 for a channel as a transistor. Consequently, the probability of breaking of a gate electrode can be reduced.
摘要翻译：要解决的问题：降低栅电极断裂的可能性。解决方案：制造半导体器件1的方法包括以下步骤：在硅衬底2的主表面上形成绝缘柱6; 在绝缘柱6的侧面上形成保护膜12; 在硅衬底2的主表面上形成硅柱4; 在硅柱4的侧面上形成栅极绝缘膜10; 以及形成分别覆盖硅柱4和绝缘柱6的侧面的第一和第二栅电极11和13，并相互接触。根据该制造方法，由于保护膜12形成在作为虚拟柱的绝缘柱6的侧表面上，因此在将晶体管的硅柱4作为晶体管进行处理时，防止了虚设柱的碎裂。因此，可以降低栅电极的断裂概率。版权所有（C）2012，JPO＆INPIT

3. 发明专利

JP2011181729A Method of manufacturing semiconductor device 审中-公开
标题翻译：制造半导体器件的方法
公开(公告)号：JP2011181729A
公开(公告)日：2011-09-15
申请号：JP2010045188
申请日：2010-03-02
申请人： Elpida Memory Inc , エルピーダメモリ株式会社
发明人： MUNETAKA YUKI , OYU SHIZUNORI
IPC分类号： H01L23/522 , H01L21/768 , H01L21/8242 , H01L27/108
摘要： PROBLEM TO BE SOLVED: To effectively prevent a short-circuiting between a wiring line and a contact plug.
SOLUTION: In a method of manufacturing a semiconductor device, a plurality of contact holes including a first contact hole where a wiring line is exposed are formed in an inter-layer insulating film positioned between adjacent wiring lines. Then a part of the exposed wiring is removed so that: (i) a side face where the wiring line is exposed is substantially flush with an inner wall side face comprised of a first insulating film of the first contact hole; or (ii) the side face where the wiring line is exposed is formed into a hollowed recess shape in the inner wall side face of the first contact hole. Then a side wall film is formed on the inner wall side face of the contact hole, and then the contact hole is filled with a conductive material to form the contact plug.
COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：有效地防止布线和接触插头之间的短路。解决方案：在制造半导体器件的方法中，在位于相邻布线之间的层间绝缘膜中形成包括布线布线的第一接触孔的多个接触孔。然后，暴露的布线的一部分被去除，使得：（i）布线被暴露的侧面与由第一接触孔的第一绝缘膜构成的内壁侧面基本齐平; 或者，（ii）在第一接触孔的内壁侧面形成有露出线的侧面形成中空的凹部形状。然后在接触孔的内壁侧面上形成侧壁膜，然后用导电材料填充接触孔以形成接触塞。版权所有（C）2011，JPO＆INPIT

4. 发明专利

JP2013105770A Semiconductor device manufacturing method 审中-公开
标题翻译：半导体器件制造方法
公开(公告)号：JP2013105770A
公开(公告)日：2013-05-30
申请号：JP2011246426
申请日：2011-11-10
申请人： Elpida Memory Inc , エルピーダメモリ株式会社
发明人： MUNETAKA YUKI , TAKAISHI YOSHIHIRO
IPC分类号： H01L21/336 , H01L21/20 , H01L21/8242 , H01L27/108 , H01L29/78
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device manufacturing method which can reduce variation in a depth direction of an upper diffusion layer of a vertical transistor.SOLUTION: A semiconductor device manufacturing method of forming an upper diffusion layer 11 composed of a silicon layer having a flat surface, comprises: selectively and excessively growing a silicon layer having a facet; and subsequently, planarizing a surface of the silicon layer by removing an excess of the silicon layer formed on the surface of an interlayer insulation film 7 by CMP. The silicon layer is grown by selectively epitaxial growing the silicon layer by a single crystal silicon. In this case, because a facet is generated, the silicon layer is excessively grown until the slowest growing facet reaches above the surface of the interlayer insulation film.
摘要翻译：要解决的问题：提供一种可以减小垂直晶体管的上部扩散层的深度方向的变化的半导体器件制造方法。解决方案：形成由具有平坦表面的硅层构成的上部扩散层11的半导体器件制造方法包括：选择性地且过度地生长具有小面的硅层; 然后通过CMP除去在层间绝缘膜7的表面上形成的过量的硅层来平坦化硅层的表面。通过用单晶硅选择性地外延生长硅层来生长硅层。在这种情况下，由于产生刻面，所以硅层过度生长，直到生长最慢的小面到达层间绝缘膜的表面以上。版权所有（C）2013，JPO＆INPIT

5. 发明专利

JP2012018976A Method for manufacturing semiconductor device 审中-公开
标题翻译：制造半导体器件的方法
公开(公告)号：JP2012018976A
公开(公告)日：2012-01-26
申请号：JP2010154010
申请日：2010-07-06
申请人： Elpida Memory Inc , エルピーダメモリ株式会社
发明人： MUNETAKA YUKI , TAKAISHI YOSHIHIRO
IPC分类号： H01L21/8242 , H01L27/108
摘要： PROBLEM TO BE SOLVED: To increase capacitor capacitance with a simple method, and also facilitate the manufacture of a contact plug formed in the same layer as a capacitor.SOLUTION: In a method for manufacturing a semiconductor device, a contact plug having a two-layer structure of a barrier film and a metal film is formed temporarily in interlayer insulating films (10 and 20) in a memory cell part, interlayer insulating films (21 and 22) are laminated on the interlayer insulating films (10 and 20), an opening exposing a top face of the contact plug is formed, and the metal film is selectively removed. Then, a lower electrode of a capacitor is formed, the lower electrode being integrated with the remaining barrier film. In a peripheral circuit part, contact plugs connecting an upper layer wiring 31 with a lower layer wiring 6B are provided in two stages (41 and 42).
摘要翻译：要解决的问题：通过简单的方法增加电容器电容，并且还有助于制造与电容器形成在同一层中的接触塞。解决方案：在制造半导体器件的方法中，在存储单元部分的中间层绝缘膜（10和20）中临时形成具有阻挡膜和金属膜的两层结构的接触插塞，夹层绝缘膜（21和22）层叠在层间绝缘膜（10和20）上，形成露出接触插塞的顶面的开口，并且选择性地去除金属膜。然后，形成电容器的下部电极，下部电极与剩余的阻挡膜一体化。在外围电路部分中，连接上层布线31和下层布线6B的接触插头设置在两个阶段（41,42）中。版权所有（C）2012，JPO＆INPIT

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