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1. 发明专利

JP2010034195A Silicon wafer, and method of manufacturing the same 有权
标题翻译：硅波及其制造方法
公开(公告)号：JP2010034195A
公开(公告)日：2010-02-12
申请号：JP2008193336
申请日：2008-07-28
申请人： Covalent Materials Corp , Toshiba Corp , Toshiba Semiconductor Service & Support Co Ltd , コバレントマテリアル株式会社 , 東芝半導体サービス&サポート株式会社 , 株式会社東芝
发明人： ISOGAI HIROMICHI , SENDA TAKESHI , MURAYAMA KUMIKO , TOYODA EIJI , SENSAI KOJI , ARAKI KOJI , AOKI TATSUHIKO , SAIDA SHIGEHIKO , TSUCHIYA NORIHIKO
IPC分类号： H01L21/322 , H01L21/26
摘要： PROBLEM TO BE SOLVED: To provide a silicon wafer the surface portion of which as a device active region includes high stress resistance and further includes crystallinity of high quality, and to provide a method of manufacturing the same.
SOLUTION: An annealed wafer or epitaxial wafer having a DZ (Denuded Zone) layer with reduced grown-in defect and BMD (Bulk Micro Defect) of COPs (Crystal Oriented Particles) etc. is subjected to a rapid temperature raising/falling heat treatment in an oxygen gas atmosphere. Then a silicon wafer is manufactured which includes a concentration distribution of oxygen in solid solution having a maximum value and a minimum value at a predetermined depth from a wafer surface along the thickness as shown by a solid line (a). The maximum value is 1.0×10
17 to 8.0×10
17 atoms/cm
3 at a depth of 0.2 to 2.0 μm from the surface, and the minimum value is 1.0×10
17 atoms/cm
3 to ≤1/5 time as large as the maximum value at a depth of 2.4 to 12 μm from the surface.
COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：为了提供作为器件有源区的表面部分包括高抗应力性的硅晶片，并且还包括高质量的结晶度，并提供其制造方法。解决方案：具有减少的生长缺陷的DZ（剥离区）层和COP（晶体取向颗粒）的BMD（Bulk Micro Defect））的退火晶片或外延晶片经受快速升温/下降在氧气气氛中进行热处理。然后，如实线（a）所示，制造硅晶片，其包括固体溶液中的氧浓度分布，其具有从晶片表面沿着厚度的预定深度处的最大值和最小值。在距表面0.2〜2.0μm的深度处，最大值为1.0×10 17 至8.0×10 17 原子/ cm 3 / SP> 最小值为距表面2.4〜12μm深度的最大值的1.0×10 17 原子/ cm 3 / SP>〜1/5倍。版权所有（C）2010，JPO＆INPIT

2. 发明专利

JP2013045978A Solid state imaging element semiconductor substrate and manufacturing method of solid state imaging element using the same 有权
标题翻译：固态成像元件半导体基板和使用其的固态成像元件的制造方法
公开(公告)号：JP2013045978A
公开(公告)日：2013-03-04
申请号：JP2011184119
申请日：2011-08-25
申请人： Covalent Materials Corp , コバレントマテリアル株式会社
发明人： ARAKI KOJI , SENDA TAKESHI , SENSAI KOJI
IPC分类号： H01L27/146 , H01L21/322 , H04N5/374
摘要： PROBLEM TO BE SOLVED: To provide a solid state imaging element semiconductor substrate applied to manufacturing of a solid state imaging element, which can achieve thinning of a film with high accuracy without an end point detection part remaining in the solid state imaging element after manufacturing and without a problem of diffusion and the like to a semiconductor element part.SOLUTION: A solid state imaging element semiconductor substrate to which backside processing from a rear face side with leaving a surface layer part on a surface side that is to be an element part formation region is applied, comprises: the surface layer part on the surface side that is to be the element part formation region; a first bulk layer formed more inside than the surface layer part in a direction toward the rear face side and to which backside processing at a BMD density of not less than 1×10/cmand not more than 1×10/cmis applied; and a second bulk layer formed more inside than the first bulk layer in a direction toward the rear face side and to which backside processing at a BMD density lower than that for the first bulk layer of not less than 1×10/cmand not more than 1×10/cmis applied.
摘要翻译：要解决的问题：提供一种应用于制造固态成像元件的固态成像元件半导体衬底，其可以以高精度实现薄膜的薄化，而不会在固态成像元件中残留终点检测部分在制造之后并且没有扩散等问题到半导体元件部分。解决方案：一种固态成像元件半导体衬底，其从背面侧进行背面处理，在作为元件部分形成区域的表面侧留下表面层部分，包括：表面层部分作为元件部分形成区域的表面侧; 在朝向背面侧的方向上比表面层部分更内侧形成的第一体积层，以及BMD密度为1×10 6/10以上的背面处理， 3 而不大于1×10 12 / cm 3 应用; 以及在朝向背面侧的方向上比第一体层更内侧形成的第二体层，BMD密度比第一体积层的BMD密度低的背面处理不小于1×10 9 / cm 3 而不大于1×10 10 / cm 3 。版权所有（C）2013，JPO＆INPIT

3. 发明专利

JP2010212333A Method of heat-treating silicon wafer 有权
标题翻译：热处理硅砂的方法
公开(公告)号：JP2010212333A
公开(公告)日：2010-09-24
申请号：JP2009054703
申请日：2009-03-09
申请人： Covalent Materials Corp , コバレントマテリアル株式会社
发明人： SENDA TAKESHI , ISOGAI HIROMICHI , TOYODA EIJI , MURAYAMA KUMIKO , ARAKI KOJI , AOKI TATSUHIKO , SUDO HARUO , SENSAI KOJI , MAEDA SUSUMU , KASHIMA KAZUHIKO
IPC分类号： H01L21/322 , C30B29/06 , C30B33/02 , H01L21/324
摘要： PROBLEM TO BE SOLVED: To provide a method of heat-treating a silicon wafer, the method eliminating a crystal defect of a COP etc., at a surface part of the wafer to become a device active region, generating a BMD at a bulk part with high density, and further suppressing a slip generated during an RTP.
SOLUTION: In the method of heat-treating the silicon wafer obtained by slicing a silicon single-crystal ingot manufactured by a Czochralski method, a rapid heating and rapid cooling heat treatment is carried out in an oxygen-containing atmosphere under a condition in which maximum reaching temperature is equal to or higher than 1,300°C and equal to or lower than the fusion point of silicon and a temperature lowering speed from the maximum reaching temperature is 50 to 145°C/second.
COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：提供一种在晶片的表面部分处理硅晶片的方法，该方法消除了COP等的晶体缺陷，以成为器件有源区，从而产生BMD在高密度的体积部分，并进一步抑制在RTP期间产生的滑动。解决方案：在通过切片通过切克劳斯基法（Czochralski）制造的硅单晶锭进行切片获得的硅晶片的热处理方法中，在含氧气氛中在条件下进行快速加热和快速冷却热处理其中最大达到温度等于或高于1300℃且等于或低于硅的熔点，并且从最大到达温度的降温速度为50至145℃/秒。版权所有（C）2010，JPO＆INPIT

4. 发明专利

JP2010073876A Silicon wafer 审中-公开
标题翻译：硅胶
公开(公告)号：JP2010073876A
公开(公告)日：2010-04-02
申请号：JP2008239434
申请日：2008-09-18
申请人： Covalent Materials Corp , コバレントマテリアル株式会社
发明人： WATANABE TAKASHI , SENSAI KOJI , ISOGAI HIROMICHI , TOYODA EIJI
IPC分类号： H01L21/02
摘要： PROBLEM TO BE SOLVED: To provide a silicon wafer which maintains high strength by allowing the control of an oxygen concentration profile with a margin in a distance from a surface when being laminated, and can suppress the generation of an oxygen donor during a device manufacturing process.
SOLUTION: In the silicon wafer, an oxygen concentration curve f(x) representing the oxygen concentration profile satisfies formulas (1) and (2) wherein x
1 is a first distance being a distance from a surface layer of the silicon wafer to the deepest portion of a first layer having the lowest first oxygen concentration a, and x
3 is a second distance being a distance from the surface layer of the silicon wafer to the shallowest portion of a second layer having the highest second oxygen concentration b.
COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：提供一种通过在层叠时允许从表面距离保持一定距离的氧浓度分布来保持高强度的硅晶片，并且可以抑制在一个设备制造过程。解决方案：在硅晶片中，表示氧浓度分布的氧浓度曲线f（x）满足公式（1）和（2），其中x 1 是距离硅晶片的表面层到具有最低的第一氧浓度a的第一层的最深部分，并且x SB 3是从硅晶片的表面层到第二层的距离的第二距离具有最高第二氧浓度的第二层的最浅部分b。版权所有（C）2010，JPO＆INPIT

5. 发明专利

JP2009253133A Method of planarizing semiconductor wafer, local plasma treatment apparatus, and method of manufacturing semiconductor wafer 有权
标题翻译：平面化半导体滤波器的方法，局部等离子体处理装置及制造半导体滤波器的方法
公开(公告)号：JP2009253133A
公开(公告)日：2009-10-29
申请号：JP2008101137
申请日：2008-04-09
申请人： Covalent Materials Corp , Shibaura Mechatronics Corp , コバレントマテリアル株式会社 , 芝浦メカトロニクス株式会社
发明人： NAKANO HARUKA , WATANABE SHIGERU , HIROSE HARUMICHI , IWAMI MUNENORI , IVAN PETROV GANASHEV , ISOGAI HIROMICHI , TOYODA EIJI , MURAYAMA KUMIKO , SENSAI KOJI
IPC分类号： H01L21/3065 , H01L21/304
摘要： PROBLEM TO BE SOLVED: To provide a method of planarizing a semiconductor wafer, a local plasma treatment apparatus, and a method of manufacturing a semiconductor wafer which can shorten the treatment time.
SOLUTION: In the method of planarizing a semiconductor wafer, an etching gas is excited by plasmas to produce a gas containing neutral active species and then the produced gas is locally supplied to the principal plane of the semiconductor wafer to locally etch the semiconductor wafer to planarize the semiconductor wafer. In the method, the in-plane surface of the semiconductor wafer is divided into a plurality of regions having a different profile of an etch rate, and a position to perform local etching is determined in each region so as to suppress a difference in profile of the etch rate among the plurality of regions.
COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：提供一种平面化半导体晶片的方法，局部等离子体处理装置以及可以缩短处理时间的半导体晶片的制造方法。解决方案：在平面化半导体晶片的方法中，通过等离子体激发蚀刻气体以产生含有中性活性物质的气体，然后将所产生的气体局部地供应到半导体晶片的主平面以局部蚀刻半导体晶片以使半导体晶片平坦化。在该方法中，半导体晶片的面内表面被划分为具有不同刻蚀速率的多个区域，并且在每个区域中确定执行局部蚀刻的位置，以便抑制轮廓的差异多个区域之间的蚀刻速率。版权所有（C）2010，JPO＆INPIT

6. 发明专利

JP2008177530A Semiconductor substrate and method of manufacturing the same 审中-公开
标题翻译：半导体基板及其制造方法
公开(公告)号：JP2008177530A
公开(公告)日：2008-07-31
申请号：JP2007277182
申请日：2007-10-25
申请人： Covalent Materials Corp , コバレントマテリアル株式会社
发明人： SENDA TAKESHI , ISOGAI HIROMICHI , TOYODA EIJI , NARITA AKIKO , SENSAI KOJI
IPC分类号： H01L21/02 , H01L21/324
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor substrate formed by joining directly semiconductor wafers having a different crystal face orientation from each other, capable of improving a property of a semiconductor device formed on its surface by improving a flatness of junction interface and reducing a surface roughness, and to provide a method of manufacturing the same.
SOLUTION: The semiconductor substrate is formed by joining directly a first semiconductor wafer and a second semiconductor wafer. A surface of one of the first semiconductor wafer and the second semiconductor wafer generally has {100} plane orientation. A surface of the other semiconductor wafer has an inclination angle (an off angle) of 0 degree or more and 0.12 degrees or less or 5 degrees or more and 11 degrees or less with respect to the {110} plane.
COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：为了提供通过直接接合具有不同晶面取向的半导体晶片形成的半导体衬底，能够通过提高结界面的平坦度来改善其表面上形成的半导体器件的性能，降低表面粗糙度，并提供其制造方法。解决方案：通过直接接合第一半导体晶片和第二半导体晶片来形成半导体衬底。第一半导体晶片和第二半导体晶片之一的表面通常具有ä100}面取向。另一半导体晶片的表面相对于ä110}面具有0度以上且0.12度以下或5度以上且11度以下的倾斜角度（偏离角）。版权所有（C）2008，JPO＆INPIT

7. 发明专利

JP2008177529A Semiconductor substrate and method for manufacturing the same 审中-公开
标题翻译：半导体基板及其制造方法
公开(公告)号：JP2008177529A
公开(公告)日：2008-07-31
申请号：JP2007277181
申请日：2007-10-25
申请人： Covalent Materials Corp , コバレントマテリアル株式会社
发明人： TOYODA EIJI , SENDA TAKESHI , NARITA AKIKO , ISOGAI HIROMICHI , SENSAI KOJI
IPC分类号： H01L21/02 , H01L21/304 , H01L21/324 , H01L29/78
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor substrate whose surface roughness is reduced by optimizing an inclination (off angle) of the semiconductor substrate surface, with respect to a ä110} plane, and to provide a method for manufacturing the semiconductor substrate. SOLUTION: This semiconductor substrate surface has the inclination (off angle) of 0 degree or larger and 0.12 degrees or smaller, or 5 degrees or larger and 11 degrees or lower, preferably 6 degrees or more and 9 degrees or smaller, with respect to the ä110} plane. This method for manufacturing the semiconductor substrate has a process, in which a semiconductor single crystal ingot is sliced at an inclination (off angle) of 5 degrees or larger and 11 degrees or less, preferably 6 degrees or more and 9 degrees or less with respect to the ä110} surface. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：解决的问题：为了通过优化相对于ä110}面的半导体衬底表面的倾斜（偏角）来提供其表面粗糙度减小的半导体衬底，并且提供一种用于制造半导体衬底的方法。解决方案：该半导体衬底表面具有0度或更大且0.12度或更小，或5度或更大和11度或更小，优选6度以上且9度或更小的倾斜度（偏离角），其中尊重ä110}飞机。这种制造半导体衬底的方法具有这样的方法，其中半导体单晶锭以5度以上且11度以下，优选6度以上且9度以下的倾斜（偏离角）切割，相对于到ä110}表面。版权所有（C）2008，JPO＆INPIT

8. 发明专利

JP2011171402A Method of heat treating silicon wafer 有权
标题翻译：热处理硅砂的方法
公开(公告)号：JP2011171402A
公开(公告)日：2011-09-01
申请号：JP2010031968
申请日：2010-02-17
申请人： Covalent Materials Corp , コバレントマテリアル株式会社
发明人： SENDA TAKESHI , ISOGAI HIROMICHI , TOYODA EIJI , ARAKI KOJI , SENSAI KOJI , AOKI TATSUHIKO , SUDO HARUO , SAITO HIROYUKI , MAEDA SUSUMU , KASHIMA KAZUHIKO
IPC分类号： H01L21/322 , C30B29/06 , C30B33/02
摘要： PROBLEM TO BE SOLVED: To provide a method of heat treating a silicon wafer reducing crystalline defects such as voids in a front surface part of a wafer serving as a device active region and suppressing elongation of slip dislocation under a load such as a thermal stress in a device process.
SOLUTION: In the method of heat treating the silicon wafer obtained by slicing a silicon monocrystalline ingot manufactured by Czochralski method, a rapid heating and rapid cooling heat treatment is performed on the silicon wafer which is at least 1.4×10
18 atoms/cm
3 in oxygen concentration under an oxygen-containing atmosphere and at a highest end-point temperature which is at least 1,325°C and not more than the melting point of the silicon.
COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：解决的问题：提供一种对硅晶片进行热处理的方法，减少了晶片的前表面部分中的诸如空隙的晶体缺陷，并且抑制了在诸如设备过程中的热应力。解决方案：在通过切割由Czochralski法制造的硅单晶锭获得的硅晶片的热处理方法中，对至少为1.4×10 的硅晶片进行快速加热和快速冷却热处理， 18 原子/ cm 3 / SP>在氧气浓度下，在最高终点温度为至少1325℃且不大于硅的熔点。版权所有（C）2011，JPO＆INPIT

9. 发明专利

JP2011103380A Compound semiconductor substrate 有权
标题翻译：化合物半导体基板
公开(公告)号：JP2011103380A
公开(公告)日：2011-05-26
申请号：JP2009257899
申请日：2009-11-11
申请人： Covalent Materials Corp , コバレントマテリアル株式会社
发明人： KOMIYAMA JUN , ISOGAI HIROMICHI , TOYODA EIJI , SUZUKI SHUNICHI , KASHIMA KAZUHIKO , SENSAI KOJI , NAKANISHI HIDEO
IPC分类号： H01L21/20 , H01L21/205
摘要： PROBLEM TO BE SOLVED: To provide a compound semiconductor substrate achieving a high level of reduction of warpage of a substrate and a high level of speed performance of a device. SOLUTION: The compound semiconductor substrate includes a substrate made of Si single crystal, an intermediate layer of nitride semiconductor formed on a main surface of the substrate, and a compound semiconductor layer of the nitride semiconductor formed on the main surface of the intermediate layer, wherein an oxygen concentration of the substrate is 0.2×10 18 to 1.4×10 18 atoms/cm 3 , a resistance value is 1000 Ωcm or higher, and a total film thickness of the intermediate layer and the compound semiconductor layer in a direction perpendicular to the main surface is 450-4500 nm. COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：提供一种化合物半导体衬底，其实现了基板的翘曲的高水平降低和装置的高水平的速度性能。解决方案：化合物半导体衬底包括由Si单晶制成的衬底，形成在衬底的主表面上的氮化物半导体的中间层和形成在中间层的主表面上的氮化物半导体的化合物半导体层层，其中，所述基板的氧浓度为0.2×10×SP×〜1.4×10×SP原子/ cm 3，SP电阻值为1000 Ωcm以上，中间层和化合物半导体层的与主面垂直的方向的总膜厚为450〜4500nm。版权所有（C）2011，JPO＆INPIT

10. 发明专利

JP2011071415A Method of manufacturing silicon wafer 审中-公开
标题翻译：制造硅波的方法
公开(公告)号：JP2011071415A
公开(公告)日：2011-04-07
申请号：JP2009222585
申请日：2009-09-28
申请人： Covalent Materials Corp , コバレントマテリアル株式会社
发明人： ISOGAI HIROMICHI , SENSAI KOJI
IPC分类号： H01L21/306 , H01L21/66
摘要： PROBLEM TO BE SOLVED: To provide a method of manufacturing a silicon wafer that is able to locally process a silicon wafer and planarize the entire silicon wafer surface with high precision and throughput, when performing the silicon wafer planarization process.
SOLUTION: The method includes the steps of measuring the size of thickness at each predetermined interval on a wafer surface to find first shape data of the silicon wafer W; performing the fast Fourier transform (FFT) on the first shape data to find a first frequency distribution; filtering the first frequency distribution by using the band-pass filter which only allows desired frequency components to pass and find a second frequency distribution; performing the inverse-Fourier transformation (IFFT) on the second frequency distribution to find the second shape data; and locally processing a section which is thicker than the reference thickness value, based on the second shape data.
COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：提供一种制造硅晶片的方法，当执行硅晶片平面化处理时，能够以高精度和高吞吐量对硅晶片进行局部处理并平整整个硅晶片表面。解决方案：该方法包括以下步骤：在晶片表面上以每个预定间隔测量厚度尺寸，以找到硅晶片W的第一形状数据; 对所述第一形状数据执行快速傅立叶变换（FFT）以找到第一频率分布; 通过使用仅允许期望的频率分量通过并找到第二频率分布的带通滤波器对第一频率分布进行滤波; 对第二频率分布执行傅立叶逆变换（IFFT）以找到第二形状数据; 并且基于第二形状数据来局部处理比参考厚度值厚的部分。版权所有（C）2011，JPO＆INPIT

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