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1. 发明专利

JP2009218735A Semiconductor integrated device 有权
标题翻译：半导体集成器件
公开(公告)号：JP2009218735A
公开(公告)日：2009-09-24
申请号：JP2008058508
申请日：2008-03-07
申请人： Toshiba Corp , Toshiba Semiconductor Service & Support Co Ltd , 東芝半導体サービス&サポート株式会社 , 株式会社東芝
发明人： NAKAMURA TETSUYA , ITO HIDEAKI
IPC分类号： H03K19/0185
CPC分类号： H03K3/35613
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor integrated device with a high-speed operating level shift circuit.
SOLUTION: The device includes the level shift circuit 11, first and second current mirror circuits 12, 13 charging first and second output nodes Nout1, Nout2, first and second switch circuits 16, 19 operating the first and second current mirror circuits 12, 13, a fifth switch element 20 parallel-connected to an input side of the first current mirror circuit 12, driven with a second output signal Vout2 and bringing charge of the first output node Nout1 to a stop early when the first switch circuit 16 stops operation of the first current mirror circuit 12 and a sixth switch element 21 parallel-connected to an input side of the second current mirror circuit 13, driven with a first output signal Vout1 and bringing charge of the second output node Nout2 to a stop early when the second switch circuit 19 stops operation of the second current mirror circuit 13.
COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：为半导体集成器件提供高速工作电平移位电路。解决方案：该装置包括电平移位电路11，第一和第二电流镜电路12,13，充电第一和第二输出节点Nout1，Nout2，操作第一和第二电流镜电路12的第一和第二开关电路16,19 ，13是与第一电流镜电路12的输入侧并联连接的第五开关元件20，由第二输出信号Vout2驱动，当第一开关电路16停止时，使第一输出节点Nout1的电荷提前停止第一电流镜电路12的工作和与第二电流镜电路13的输入侧并联连接的第六开关元件21，由第一输出信号Vout1驱动，并使第二输出节点Nout2的电荷提前停止第二开关电路19停止第二电流镜电路13的操作。版权所有（C）2009，JPO＆INPIT

2. 发明专利

JP2010034195A Silicon wafer, and method of manufacturing the same 有权
标题翻译：硅波及其制造方法
公开(公告)号：JP2010034195A
公开(公告)日：2010-02-12
申请号：JP2008193336
申请日：2008-07-28
申请人： Covalent Materials Corp , Toshiba Corp , Toshiba Semiconductor Service & Support Co Ltd , コバレントマテリアル株式会社 , 東芝半導体サービス&サポート株式会社 , 株式会社東芝
发明人： ISOGAI HIROMICHI , SENDA TAKESHI , MURAYAMA KUMIKO , TOYODA EIJI , SENSAI KOJI , ARAKI KOJI , AOKI TATSUHIKO , SAIDA SHIGEHIKO , TSUCHIYA NORIHIKO
IPC分类号： H01L21/322 , H01L21/26
摘要： PROBLEM TO BE SOLVED: To provide a silicon wafer the surface portion of which as a device active region includes high stress resistance and further includes crystallinity of high quality, and to provide a method of manufacturing the same.
SOLUTION: An annealed wafer or epitaxial wafer having a DZ (Denuded Zone) layer with reduced grown-in defect and BMD (Bulk Micro Defect) of COPs (Crystal Oriented Particles) etc. is subjected to a rapid temperature raising/falling heat treatment in an oxygen gas atmosphere. Then a silicon wafer is manufactured which includes a concentration distribution of oxygen in solid solution having a maximum value and a minimum value at a predetermined depth from a wafer surface along the thickness as shown by a solid line (a). The maximum value is 1.0×10
17 to 8.0×10
17 atoms/cm
3 at a depth of 0.2 to 2.0 μm from the surface, and the minimum value is 1.0×10
17 atoms/cm
3 to ≤1/5 time as large as the maximum value at a depth of 2.4 to 12 μm from the surface.
COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：为了提供作为器件有源区的表面部分包括高抗应力性的硅晶片，并且还包括高质量的结晶度，并提供其制造方法。解决方案：具有减少的生长缺陷的DZ（剥离区）层和COP（晶体取向颗粒）的BMD（Bulk Micro Defect））的退火晶片或外延晶片经受快速升温/下降在氧气气氛中进行热处理。然后，如实线（a）所示，制造硅晶片，其包括固体溶液中的氧浓度分布，其具有从晶片表面沿着厚度的预定深度处的最大值和最小值。在距表面0.2〜2.0μm的深度处，最大值为1.0×10 17 至8.0×10 17 原子/ cm 3 / SP> 最小值为距表面2.4〜12μm深度的最大值的1.0×10 17 原子/ cm 3 / SP>〜1/5倍。版权所有（C）2010，JPO＆INPIT

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