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    • 1. 发明专利
    • Cell culture carrier
    • 细胞培养载体
    • JP2010063378A
    • 2010-03-25
    • JP2008230686
    • 2008-09-09
    • Covalent Materials Corpコバレントマテリアル株式会社
    • IMAIZUMI YUKIFUMINAKANISHI HIDEO
    • C12M3/00
    • C12M23/12
    • PROBLEM TO BE SOLVED: To provide a cell culture carrier which can stably adhere cells to dents and can more three-dimensionally culture the cells.
      SOLUTION: The cell culture carrier includes the first substrate 2 formed from a compact material, and the second substrate 3 which is laminated to the first substrate 2 and in which a plurality of dents 5 having openings 4 in the lamination direction α are disposed in a direction α parallel to the surface 2A of the first substrate 2, wherein each dent 5 is formed of a bottom portion 5A composed of the first substrate 2 and a side portion 5B which is composed of the second substrate 3 and whose at least surface is porous.
      COPYRIGHT: (C)2010,JPO&INPIT
    • 待解决的问题:提供一种细胞培养载体,其可以将细胞稳定地粘附到凹陷上,并且可以更多地三维培养细胞。 解决方案:细胞培养载体包括由致密材料形成的第一基底2和层叠到第一基底2上的第二基底3,并且其中具有层叠方向α上的开口4的多个凹痕5是 设置在与第一基板2的表面2A平行的方向α上,其中每个凹部5由由第一基板2构成的底部5A和由第二基板3构成的侧部5B形成,并且至少 表面是多孔的。 版权所有(C)2010,JPO&INPIT
    • 4. 发明专利
    • Compound semiconductor device
    • 化合物半导体器件
    • JP2007266151A
    • 2007-10-11
    • JP2006086844
    • 2006-03-28
    • Covalent Materials Corpコバレントマテリアル株式会社
    • KOMIYAMA JUNABE YOSHIHISASUZUKI SHUNICHINAKANISHI HIDEO
    • H01L29/12H01L21/336H01L29/739H01L29/78
    • PROBLEM TO BE SOLVED: To provide a highly efficient compound semiconductor device with less energy loss. SOLUTION: An n-type low carrier concentration layer 2 with a carrier concentration as ≥10 11 /cm 3 and ≤10 16 /cm 3 , a p-type layer 3 with the carrier concentration as ≥10 11 /cm 3 and ≤10 21 /cm 3 , and an n-type high carrier concentration layer 4 with the carrier concentration ≥10 16 /cm 3 and ≤10 21 /cm 3 , are sequentially laminated on a low resistance substrate 1. The respective layers 2-4 are made to be 3C-SiC single crystal with the fault density of not more than 10 4 /cm 2 concerning a micropipe, a double-positioning domain, an anti-phase domain, a stacking fault, and a twin band. The compound semiconductor device also includes: a gate insulating film 5 which contacts at least the p-type layer 3, a control electrode 6 which contacts the gate insulating film 5 and is electrically separated from the respective layers 2-4, an upper electrode 7 which contacts at least the p-type layer 3 and the n-type high carrier concentration layer 4, and a lower electrode 8 which contacts the low resistance substrate 1. COPYRIGHT: (C)2008,JPO&INPIT
    • 要解决的问题:提供具有较少能量损失的高效化合物半导体器件。

      解决方案:载流子浓度为≥10 11 / cm 3 和≤10 16 的n型低载流子浓度层2 载体浓度为≥10 11 / cm 3 和≤10 21

      的p型层3, / SP> / cm 3 / SP>,载流子浓度≥10 16 / cm 3的n型高载流子浓度层4和≤ 10 21 / cm 3 顺序层压在低电阻基板1上。各层2-4被制成3C-SiC单晶,其故障密度 关于微管,双定位域,反相域,堆垛层错和双频带的不超过10 4 / cm 2 。 复合半导体器件还包括:至少与p型层3接触的栅极绝缘膜5,与栅极绝缘膜5接触并与各层2-4电气分离的控制电极6,上部电极7 其至少接触p型层3和n型高载流子浓度层4,以及与低电阻基板1接触的下电极8.版权所有(C)2008,JPO&INPIT

    • 5. 发明专利
    • Compound semiconductor substrate
    • 化合物半导体基板
    • JP2011103380A
    • 2011-05-26
    • JP2009257899
    • 2009-11-11
    • Covalent Materials Corpコバレントマテリアル株式会社
    • KOMIYAMA JUNISOGAI HIROMICHITOYODA EIJISUZUKI SHUNICHIKASHIMA KAZUHIKOSENSAI KOJINAKANISHI HIDEO
    • H01L21/20H01L21/205
    • PROBLEM TO BE SOLVED: To provide a compound semiconductor substrate achieving a high level of reduction of warpage of a substrate and a high level of speed performance of a device. SOLUTION: The compound semiconductor substrate includes a substrate made of Si single crystal, an intermediate layer of nitride semiconductor formed on a main surface of the substrate, and a compound semiconductor layer of the nitride semiconductor formed on the main surface of the intermediate layer, wherein an oxygen concentration of the substrate is 0.2×10 18 to 1.4×10 18 atoms/cm 3 , a resistance value is 1000 Ωcm or higher, and a total film thickness of the intermediate layer and the compound semiconductor layer in a direction perpendicular to the main surface is 450-4500 nm. COPYRIGHT: (C)2011,JPO&INPIT
    • 要解决的问题:提供一种化合物半导体衬底,其实现了基板的翘曲的高水平降低和装置的高水平的速度性能。 解决方案:化合物半导体衬底包括由Si单晶制成的衬底,形成在衬底的主表面上的氮化物半导体的中间层和形成在中间层的主表面上的氮化物半导体的化合物半导体层 层,其中,所述基板的氧浓度为0.2×10×SP×〜1.4×10×SP原子/ cm 3,SP电阻值为1000 Ωcm以上,中间层和化合物半导体层的与主面垂直的方向的总膜厚为450〜4500nm。 版权所有(C)2011,JPO&INPIT
    • 7. 发明专利
    • Compound semiconductor substrate
    • 化合物半导体基板
    • JP2009065082A
    • 2009-03-26
    • JP2007233818
    • 2007-09-10
    • Covalent Materials Corpコバレントマテリアル株式会社
    • KOMIYAMA JUNYOSHIDA AKIRAOISHI KOJIABE YOSHIHISASUZUKI SHUNICHINAKANISHI HIDEO
    • H01L21/20H01L21/205
    • PROBLEM TO BE SOLVED: To provide a compound semiconductor substrate having a nitride semiconductor single crystal layer suitable for a high speed and high breakdown voltage device by controlling carriers remaining in a compound semiconductor single crystal layer.
      SOLUTION: On an Si single crystal substrate 1, a 3C-SiC single crystal buffer layer 2 with a thickness of 0.05-2 μm containing at least any one impurity element out of B, Al, V, Ni, Fe, Mg, Pt, Cr, Mo, W, Ta, Nb, Sc, Ti, Au, Co and Cu by 10
      14 -10
      21 /cm
      3 , and a GaN single crystal buffer layer 3 with a thickness of 0.05-5 μm containing at least any one impurity element out of C, V, Ni, Fe, Mg, Pt, Cr, Mo, W, Ta, Nb, Sc, Ti, Au, Co and Cu by 10
      14 -10
      21 /cm
      3 are laminated sequentially.
      COPYRIGHT: (C)2009,JPO&INPIT
    • 解决的问题:通过控制残留在化合物半导体单晶层中的载流子,提供具有适用于高速和高击穿电压器件的氮化物半导体单晶层的化合物半导体衬底。 解决方案:在Si单晶衬底1上,含有至少含有B,Al,V,Ni,Fe,Mg中的任何一种杂质元素的厚度为0.05-2μm的3C-SiC单晶缓冲层2 ,Pt,Cr,Mo,W,Ta,Nb,Sc,Ti,Au,Co和Cu中的至少一种。 以及包含C,V,Ni,Fe,Mg,Pt,Cr,Mo,W,Ta,Nb中的至少一种杂质元素的厚度为0.05-5μm的GaN单晶缓冲层3, Sc,Ti,Au,Co和Cu依次层叠10×SP 14 / SP 3 -10 / SP 3 / cm 3。 版权所有(C)2009,JPO&INPIT