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2. 发明专利

JP2004282783A Control type slew rate output buffer 有权
公开(公告)号：JP2004282783A
公开(公告)日：2004-10-07
申请号：JP2004142466
申请日：2004-05-12
申请人： Natl Semiconductor Corp , ナショナルセミコンダクタコーポレイションNational Semiconductor Corporation
发明人： BROWN MICHAEL A
IPC分类号： G11C11/409 , H03F1/00 , H03K5/12 , H03K17/60 , H03K19/003 , H03K19/0175 , H03K19/088
CPC分类号： H03K19/00376 , H03K19/00361
摘要： PROBLEM TO BE SOLVED: To provide a control type slew rate output buffer for repeating, i.e., reproducing an input signal to the output node of the output buffer.
SOLUTION: The output buffer includes: an input stage; a charging stage; a discharging stage; a hold-down stage; and an output stage. The output stage is connected between a first node and the output node and follows the slew rate in the first node during the period of the charging stage and the discharging stage. Consequently, the ascending and descending slew rates of an output signal in the output node are substantially equal to the ascending and descending slew rates of the first node.
COPYRIGHT: (C)2005,JPO&NCIPI

3. 发明专利

JP2001326571A MULTIINPUT AND CIRCUIT 失效
公开(公告)号：JP2001326571A
公开(公告)日：2001-11-22
申请号：JP2000185452
申请日：2000-05-17
申请人： NISHI JOJI
发明人： NISHI JOJI
IPC分类号： H03K19/088
摘要： PROBLEM TO BE SOLVED: To provide an electronic circuit turning an output potential from zero to a positive potential only when all the inputs become the positive potential. SOLUTION: Only when all the inputs of input signals I1 to In become the positive potential, the potential of an output 01 becomes positive. When any one of the input signals is the zero potential, the base input of a transistor TR50 is turned to be the positive potential by the positive potential of the loading resistor R1 to Rn of one of transistors TR1 to TRn to make the transistor TR50 conductive and the potential of the output 01 becomes the zero potential due to voltage dropping of a loading resistor R50. When all the potentials of the signals I1 to In become positive, all the transistors TR1 to TRn become conductive, each collector potential become zero due to voltage dropping of the collector loading resistors R1 to Rn. The base input of the transistor TR50 becomes zero, the transistor TR50 is not conductive, voltage dropping of a loading resistor R50 is eliminated and the potential of the output becomes positive. Diodes D1 to Dn are for preventing the mutual interference of the outputs of diode TR1 to TRn.

4. 发明专利

JP3209812B2 失效
公开(公告)号：JP3209812B2
公开(公告)日：2001-09-17
申请号：JP32468092
申请日：1992-11-11
IPC分类号： H03K19/0175 , H03K19/00 , H03K19/08 , H03K19/088 , H03K19/094 , H03K19/0944

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