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1. 发明专利

JP2005086099A Flip chip bga 审中-公开
标题翻译： FLIP芯片BGA
公开(公告)号：JP2005086099A
公开(公告)日：2005-03-31
申请号：JP2003318644
申请日：2003-09-10
申请人： Subtron Technology Co Ltd , サブトロンテクノロジーカンパニーリミテッド
发明人： TEI SHINKA , HO CHUNG WEN
IPC分类号： H01L23/12
摘要： PROBLEM TO BE SOLVED: To provide a flip chip BGA packaging construction by which higher electrical performance is attained by a thinner package. SOLUTION: A metal substrate includes an opening for chip placement having a chip placement region, a distribution region and a vacuum region. The distribution region and the vacuum region are arranged to adjoin each other at an opposite corner as a pair of regions with the chip placement region, a thin-film interconnecting layer is formed on the metal substrate, a BUM layer is formed on the thin-film interconnecting layer, a flip chip is disposed at the chip placement opening and is electrically connected by the thin-film interconnecting layer and a bump, and a solder mask layer is formed on the BUM layer. The solder mask layer exposes a part of a trace layer of the BUM layer at a portion farthest from the metal substrate, fills a gap between the bump and the flip chip with a underfill, and electrically connect a solder ball with the trace layer exposed by the solder mask layer. COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：提供一种倒装芯片BGA封装结构，通过更薄的封装获得更高的电气性能。解决方案：金属基板包括用于芯片放置的开口，其具有芯片放置区域，分布区域和真空区域。分布区域和真空区域被布置成在具有芯片放置区域的一对区域的相对角处彼此邻接，在金属基板上形成薄膜互连层，在薄膜上形成BUM层，薄膜互连层，倒装芯片设置在芯片放置开口处，并通过薄膜互连层和凸块电连接，并且在BUM层上形成焊料掩模层。焊接掩模层在距离金属基板最远的部分暴露BUM层的迹线层的一部分，用底部填充物填充凸块和倒装芯片之间的间隙，并将焊球与由焊接掩模层。版权所有（C）2005，JPO＆NCIPI

2. 发明专利

JP2011258909A Manufacturing method of circuit board 审中-公开
标题翻译：电路板制造方法
公开(公告)号：JP2011258909A
公开(公告)日：2011-12-22
申请号：JP2010202113
申请日：2010-09-09
申请人： Subtron Technology Co Ltd , 旭徳科技股▲ふん▼有限公司
发明人： CHUANG JI-KWING , CHEN JUNQING
IPC分类号： H01L23/12 , H05K3/00
摘要： PROBLEM TO BE SOLVED: To provide a manufacturing method of a circuit board which effectively improves positioning accuracy in laser etching process.SOLUTION: There is provided one of manufacturing methods of a circuit board, in which a board 210 is provided, and the board includes a dielectric layer 212, a first conductive layer 214, and a second conductive layer 216, and the first conductive layer and the second conductive layer are disposed on a first surface and a second surface, which are opposite surfaces of the dielectric layer, respectively. A through hole 218 is formed on the board. In the first conductive layer, an opening 214a is formed so as to expose a portion of the dielectric layer. On the dielectric layer, a sealing layer 220 is formed, which covers the through hole and portions of the first conductive layer adjacent to the through hole, and which seals an open end of the through hole adjacent to the first conductive layer. By performing laser etching on portions located below the opening of the conductive layer to form a recess in the dielectric layer so as to expose a portion of the second conductive layer, and during laser etching of the dielectric layer, the board is fixed by means of a vacuum suction method.
摘要翻译：要解决的问题：提供一种有效提高激光蚀刻工艺中的定位精度的电路板的制造方法。提供了一种电路板的制造方法之一，其中设置有基板210，并且该基板包括电介质层212，第一导电层214和第二导电层216，并且第一导电层和第二导电层分别设置在与电介质层相对的第一表面和第二表面上。通孔218形成在板上。在第一导电层中，形成开口214a以露出电介质层的一部分。在电介质层上形成密封层220，该密封层220覆盖通孔和第一导电层的与通孔相邻的部分，并且密封与第一导电层相邻的通孔的开口端。通过对位于导电层的开口下方的部分进行激光蚀刻，在电介质层中形成凹部，露出第二导电层的一部分，在电介质层的激光蚀刻期间，通过真空抽吸法。版权所有（C）2012，JPO＆INPIT

3. 发明专利

JP2011176252A Method of making fine-pitch circuit traces 审中-公开
标题翻译：制造精细电路轨迹的方法
公开(公告)号：JP2011176252A
公开(公告)日：2011-09-08
申请号：JP2010067643
申请日：2010-03-24
申请人： Subtron Technology Co Ltd , 旭▲徳▼科技股▲分▼有限公司
发明人： WU CHIEN-NAN , HUANG GUAN-WEI
IPC分类号： H05K3/06
CPC分类号： H05K3/06 , C23F1/02 , C23F1/14 , C23F1/44
摘要： PROBLEM TO BE SOLVED: To provide a method of making fine-pitch circuit traces.
SOLUTION: A method of making fine-pitch circuit traces includes the steps of: preparing an insulative substrate 10 and disposing a conductive metal layer 20 on the insulative substrate 10; disposing on a whole or a part of a top surface of the conductive metal layer 20, a hetero layer 30 having an etching rate smaller than that of the conductive metal layer 20; continuously forming a mask 40 having a circuit trace pattern on the hetero layer 30 and performing wet etching; and finally removing the mask 40 and the hetero layer 30 so as to form fine-pitch circuit traces having a high etching factor.
COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：提供制造精细间距电路迹线的方法。解决方案：制作精细间距电路迹线的方法包括以下步骤：制备绝缘衬底10并在绝缘衬底10上设置导电金属层20; 设置在导电金属层20的整个或一部分顶表面上，具有蚀刻速率小于导电金属层20的蚀刻速率的异质层30; 在异质层30上连续地形成具有电路迹线图案的掩模40，并执行湿蚀刻; 最后去除掩模40和异质层30，以形成具有高腐蚀因子的细间距电路迹线。版权所有（C）2011，JPO＆INPIT

4. 发明专利

JP2014036222A Package carrier and manufacturing method therefor 有权
标题翻译：包装及其制造方法
公开(公告)号：JP2014036222A
公开(公告)日：2014-02-24
申请号：JP2013011674
申请日：2013-01-25
申请人： Subtron Technology Co Ltd , 旭徳科技股▲ふん▼有限公司
发明人： SON SEO HO
IPC分类号： H01L23/12 , H01L23/14 , H01L23/32
CPC分类号： H05K3/42 , H01L21/447 , H01L21/486 , H01L23/49827 , H01L33/642 , H01L2224/16225 , H01L2224/16227 , H01L2924/00014 , H01L2924/15311 , Y10T29/49165 , H01L2224/0401
摘要： PROBLEM TO BE SOLVED: To provide a package carrier which increases the use reliability, by reducing thermal expansion difference effectively when the package carrier is mounting a heating element, and to provide a manufacturing method therefor.SOLUTION: An insulating substrate having an upper surface, a lower surface, a plurality of cavities installed on the lower surface, and a plurality of through holes communicating, respectively, with the cavities by passing through the insulating substrate is provided. A plurality of vias are defined by the cavities and through holes. A plurality of conductive posts are defined by forming a conductive material filling the vias. An insulating layer having a top face and a plurality of blind vias extending from the top face to the conductive post is formed on the upper surface. A patterning circuit layer filling the blind vias, connected with the conductive post, and exposing a part of the top face is formed on the top face. A solder mask layer having a plurality of openings for defining a plurality of pads by exposing a part of the patterning circuit layer is formed on the patterning circuit layer.
摘要翻译：要解决的问题：提供一种提高使用可靠性的封装载体，通过在封装载体安装加热元件时有效降低热膨胀差异，并提供其制造方法。解决方案：具有上表面的绝缘基板，提供了安装在下表面上的下表面，多个空腔以及分别通过绝缘基板与空腔连通的多个通孔。多个通孔由空腔和通孔限定。通过形成填充通孔的导电材料来限定多个导电柱。在上表面上形成具有顶表面和从顶面延伸到导电柱的多个盲通孔的绝缘层。填充与导电柱连接的盲通孔并暴露顶面的一部分的图案化电路层形成在顶面上。在图案化电路层上形成具有用于通过暴露图案形成电路层的一部分来限定多个焊盘的多个开口的焊接掩模层。

5. 发明专利

JP2011228617A Circuit board and method for producing the same 审中-公开
标题翻译：电路板及其制造方法
公开(公告)号：JP2011228617A
公开(公告)日：2011-11-10
申请号：JP2010211923
申请日：2010-09-22
申请人： Subtron Technology Co Ltd , 旭徳科技股▲ふん▼有限公司
发明人： HUANG ZI WEI
IPC分类号： H05K3/00
CPC分类号： H05K3/4652 , B23K11/11 , B23K2201/42 , B32B37/0084 , B32B37/02 , B32B37/04 , B32B38/04 , B32B38/10 , B32B2038/047 , B32B2307/202 , B32B2307/206 , B32B2311/00 , B32B2311/12 , B32B2457/00 , B32B2457/08 , H05K1/115 , H05K3/0052 , H05K3/0097 , H05K3/02 , H05K3/421 , H05K3/423 , H05K3/427 , H05K3/46 , H05K3/462 , H05K3/4682 , H05K2201/09509 , H05K2201/09527 , H05K2201/09563 , H05K2201/09918 , H05K2203/1536 , H05K2203/1572 , Y10T29/49126 , Y10T29/49155 , Y10T29/49156 , Y10T29/49165
摘要： PROBLEM TO BE SOLVED: To provide a method for producing a circuit board, reducing the time consumption of the production method and improving reliability.SOLUTION: A method for producing a circuit board includes the steps of: bonding the peripheries of two metal layers to form a sealed area; forming two insulating layers on the two metal layers; forming two conductive layers on the two insulating layers, the conductive layers including upper and bottom portions; laminating the two insulating layers and the two conductive layers to embed the two metal layers, which are bonded to each other, between the two insulating layers; removing a part of the two insulating layers and a part of the two conductive layers to form a plurality of blind holes exposing the two metal layers; forming a conductive material in the blind holes and on the remaining two conductive layers; and separating the sealed area of the two metal layers to form two separate circuit boards.
摘要翻译：要解决的问题：提供一种生产电路板的方法，减少生产方法的时间消耗和提高可靠性。解决方案：一种电路板的制造方法，包括以下步骤：将两个金属层的周边粘接形成密封区域; 在两个金属层上形成两个绝缘层; 在两个绝缘层上形成两个导电层，导电层包括上部和底部; 层叠两个绝缘层和两个导电层以将两个彼此结合的两个金属层嵌入两个绝缘层之间; 去除所述两个绝缘层的一部分和所述两个导电层的一部分以形成暴露所述两个金属层的多个盲孔; 在盲孔和剩余的两个导电层上形成导电材料; 并分离两个金属层的密封区域以形成两个单独的电路板。版权所有（C）2012，JPO＆INPIT

6. 发明专利

JP2014228270A 放熱板有权
标题翻译：散热器
公开(公告)号：JP2014228270A
公开(公告)日：2014-12-08
申请号：JP2013189365
申请日：2013-09-12
申请人：旭徳科技股▲ふん▼有限公司 , Subtron Technology Co Ltd
发明人： CHEN CHING-SHENG
IPC分类号： F28D15/02 , H01L33/64
CPC分类号： F28D15/046 , F28F21/04 , H01L23/3735 , H01L23/427 , H01L2224/48091 , H01L2224/48137 , H01L2924/00014
摘要：【課題】より優れた放熱効果を達成することのできる放熱板を提供する。【解決手段】放熱板は、熱伝導性材料層と、第1金属層と、金属基板と、金属リングフレームとを含む。熱伝導性材料層は、互いに向かい合う上表面と下表面を有する。熱伝導性材料層の材料は、セラミックまたはシリコンゲルマニウムを含む。第1金属層は、熱伝導性材料層の下表面に配置され、第1粗表面構造を有する。金属基板は、第1金属層の下方に配置され、第2粗表面構造を有する。金属リングフレームは、第1金属層と金属基板の間に配置される。第1粗表面構造、金属リングフレームおよび第2粗表面構造は、流体チャンバーを定義し、この流体チャンバー内に作動流体が流入する。【選択図】図1
摘要翻译：要解决的问题：提供一种实现更优异的散热效果的散热器。解决方案：散热器包括：导热材料层; 第一金属层; 金属基板; 和金属环框架。导热材料层包括彼此面对的上表面和下表面。导热材料层的材料含有陶瓷或硅 - 锗。第一金属层设置在导热材料层的下表面上并具有第一粗糙表面结构。金属基板设置在第一金属层下方并具有第二粗糙表面结构。金属环框架设置在第一金属层和金属基板之间。第一粗糙表面结构，金属环框架和第二粗糙表面结构限定流体室，并且工作流体在流体室中流动。

7. 发明专利

JP2014107542A Package carrier 有权
标题翻译：包装载体
公开(公告)号：JP2014107542A
公开(公告)日：2014-06-09
申请号：JP2013129415
申请日：2013-06-20
申请人： Subtron Technology Co Ltd , 旭徳科技股▲ふん▼有限公司
发明人： WANG CHIN-SHENG , CHEN CHIEN-MING
IPC分类号： H01L23/12 , H01L23/36
CPC分类号： H05K1/0206 , H01L2924/0002 , H05K2201/10416 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a package carrier which is adapted to carry at least one heating element.SOLUTION: The package carrier includes a substrate, first and second insulation layers, first and second patterned circuit layers, at least one first and second conductive through holes, a heat dissipation channel, an adhesive layer and a heat conducting element. The first and second patterned circuit layers are respectively disposed on the first and second insulation layers which are respectively disposed on upper and lower surfaces of the substrate. The heat dissipation channel at least passes through the first and second insulation layers, the first patterned circuit layer and the substrate. The first and second conductive through holes electrically connect the substrate and the first and second patterned circuit layers. Each of at least two opposite side surfaces of the heat conducting element includes at least one convex portion or at least one concave portion. The heat conducting element is mounted in the heat dissipation channel via the adhesive layer.
摘要翻译：要解决的问题：提供适于承载至少一个加热元件的封装载体。解决方案：封装载体包括衬底，第一和第二绝缘层，第一和第二图案化电路层，至少一个第一和第二导电通孔，散热通道，粘合剂层和导热元件。第一和第二图案化电路层分别设置在分别设置在基板的上表面和下表面上的第一绝缘层和第二绝缘层上。散热通道至少穿过第一和第二绝缘层，第一图案化电路层和基板。第一和第二导电通孔电连接基板和第一和第二图案化电路层。导热元件的至少两个相对侧表面中的每一个包括至少一个凸部或至少一个凹部。导热元件通过粘合剂层安装在散热通道中。

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