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81. 发明专利

JPH08148947A COMMON BASE TRANSISTOR AMPLIFIER 失效
公开(公告)号：JPH08148947A
公开(公告)日：1996-06-07
申请号：JP15623295
申请日：1995-06-22
申请人： ALPS ELECTRIC CO LTD , HITACHI LTD
发明人： OKAZAKI MITSUYA , WATANABE KAZUO , ENDO TAKEFUMI
IPC分类号： H03F1/26 , H03F3/04 , H03F3/19 , H03F3/45
摘要： PURPOSE: To provide a common base transistor amplifier provided with extremely low noise figure(NF) characteristics by almost completely cancelling a noise voltage generated in the transistor of a constant current circuit. CONSTITUTION: This amplifier is provided with a pair of the transistors 1 and 2 whose base is high frequency grounded and collector is connected to a signal output terminal 16, a high frequency transformer 10 provided with a primary winding wire 10p connected to a signal input terminal 15 and a secondary winding wire 10s provided with a middle point tap 10t for which both ends of the secondary winding wire 10s are respectivelly connected to the emitters of the pair of the transistors 1 and 2 and the constant current circuit connected to the middle point tap 10t of the secondary winding wire 10s for making a bias current flow to the transistors 1 and 2. In this case, since the noise voltage generated in the transistor 7 of the constant current circuit is inputted through the secondary winding wire 10s to the emitters of the transistors 1 and 2 by common-mode, the noise voltage does not appear in the signal output terminal 16.

82. 发明专利

JPH05227031A INTEGRATION TYPE A/D CONVERSION CIRCUIT 失效
公开(公告)号：JPH05227031A
公开(公告)日：1993-09-03
申请号：JP5669692
申请日：1992-02-08
申请人： HITACHI LTD , HITACHI MICOM SYST KK
发明人： YONETANI HIROYUKI , WATANABE KAZUO
IPC分类号： H03M1/20 , H03M1/52
摘要： PURPOSE:To accurately set up a proper dither quantity by means of simple timing control by providing the integration type A/D conversion circuit with a dither current source set up with a prescribed ratio to the current value of an integration constant current source and controlling a dither injection quantity in accordance with the injection time of a dither current. CONSTITUTION:During the low level period of a control signal SH, an analog input voltage AV is fetched in to a capacitor C1. When the signal SH is changed to a high level and a switch SW1 is switched to an off state, a reset pulse RP is generated and a counter circuit CNT is reset. When the pulse RP is turned to a low level, a switch SW2 is turned on and integrating operation based on a constant current Io and the discharge of a capacitor C1 are started. At the time, a dither pulse DTH is generated, a switch SW3 is turned on and a dither current Id is added to an integration current. When the output voltage of an operational amplifier A1 reaches a reference voltage VR2, an AND gate circuit G1 is closed and counting is stopped.

83. 发明专利

JPH03240168A GRAPHIC DATA RETRIEVING/STORING METHOD 失效
公开(公告)号：JPH03240168A
公开(公告)日：1991-10-25
申请号：JP3603890
申请日：1990-02-19
申请人： HITACHI LTD , HITACHI SEIKO KK
发明人： KAKUMOTO SHIGERU , KATO KATSUYASU , OTSU FUMITAKA , WATANABE KAZUO
IPC分类号： G06F17/30 , G06T1/00 , G06T11/80
摘要： PURPOSE:To improve the availability of a memory by storing the store address of the graphic data in an address data table of a multi-dimensional array corresponding to the position coordinates and using indirectly the memory area of an unused address data table. CONSTITUTION:An address data table 11 is set opposite to the graphic data having a spatial spread, and the table 11 consists of an array having a dimension larger than the spread of the graphic data. The stored destination address of a graphic data table 12 storing each graphic data is stored in the table 11. When the memory area of the table 1 corresponding to an optional cell 14 is filled with data, the relative information used for indirect application of the memory areas allocated to other cells 14 is stored in the table 11 instead together with the store destination address of the table 12. Thus the availability of the table 11 is improved.

84. 发明专利

JPH0333795A METHOD AND DEVICE FOR DISPLAYING ENLARGED DIAGRAM 失效
公开(公告)号：JPH0333795A
公开(公告)日：1991-02-14
申请号：JP16671089
申请日：1989-06-30
申请人： HITACHI LTD , HITACHI INF & CONTROL SYST , HITACHI SEIKO KK
发明人： IWAMURA KAZUAKI , KIKUCHI YASUYUKI , KATO KATSUYASU , WATANABE KAZUO
IPC分类号： G09G5/36 , G06F3/048 , G06F3/14 , G06F17/30 , G06T1/00 , G09G3/20 , G09G5/377
摘要： PURPOSE:To display an enlarged diagram with a maximum magnification so that an enlargement object area and a window cannot overlap by placing the enlargement object area in the center of a display area, multiplying an enlargement ratio to the enlargement object area with a window calculating circuit and calculating the size of the window. CONSTITUTION:The device is composed of a display deciding circuit 102 to decide whether to execute a partial enlargement or not, an enlargement object area calculating circuit 103, a display candidate area calculating circuit 104, an enlargement ratio calculating circuit 105, a window calculating circuit 106, and a history arrangement calculating circuit 110. Further, the circuits are connected through a graphic editing circuit 107 and an I/O device 108 to a memory device 109, a display device (display) 111, a graphic input device 112, a graphic instructing device 113 and a graphic data storage device 114. In such a case, for the size of the window to enlarge and display the enlargement object area, the enlargement ratio of the enlargement object area is obtained as to the area made into the display candidate, and the window is placed in the display candidate area in which the enlargement ratio is made maximum among them. Thus, even when the shape of the enlargement object area is changed, the display can be always executed with the maximum enlargement ratio.

85. 发明专利

JPH0227401A OFFSETTING CONTROL CIRCUIT 失效
公开(公告)号：JPH0227401A
公开(公告)日：1990-01-30
申请号：JP17681488
申请日：1988-07-15
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG
发明人： YONETANI HIROYUKI , WATANABE KAZUO
IPC分类号： G05B1/02 , H03F3/34 , H03F3/347
摘要： PURPOSE:To automatically correct the offsetting of a comparator, a differential amplifier circuit and the like without using an external terminal in an LSI internal part by correcting the input level of a controlled circuit by the correcting level set automatically so as to make the offsetting of the controlled circuit into zero. CONSTITUTION:When an initializing signal Is is set to H level, the comparing input of a comparator 1 which is a controlled circuit and the reference input are mutually shorted to the same potential and a comparing output Co is switched to the detecting input side of an output change detecting circuit 3. When a resetting signal Rs is given, an output level I of a variable level generating circuit 4 is continuously changed and added to the reference input level of a comparator 1 by a level control circuit 5. When the input level passes through a point which becomes an offsetting zero, the output change detecting circuit 3 switches a detecting output Do from H level to L level simultaneously when the comparing output Co is changed and stops the stepping action of a counter 41. Thus, the input offset of the comparator 1 is automatically corrected.

86. 发明专利

JPH01287784A IMAGE PROCESSOR 失效
公开(公告)号：JPH01287784A
公开(公告)日：1989-11-20
申请号：JP11711888
申请日：1988-05-16
申请人： HITACHI LTD , HITACHI SEIKO KK
发明人： KAKUMOTO SHIGERU , WATANABE KAZUO , OYAMA MITSUO
IPC分类号： G06T5/20
摘要： PURPOSE:To perform mask arithmetic efficiently with small memory capacity by providing an auxiliary memory which can be accessed simultaneously with an image memory and holds one column of dimensional data in the image memory. CONSTITUTION:The mask arithmetic processing is processing for determining an aimed picture element value according to circumferential picture element information on an aimed picture element and also processing for scanning 3X3 (9 in total) picture elements on the image memory 301. For the purpose, part of dimensional data at a current scanning position is used even at a next scanning position. For the purpose, the auxiliary memory 302 holds the dimensional data temporarily until a next scan is finished. In this case, the amount of data which are held is unchanged even if the number of picture elements which are processed in parallel increases. Consequently, the parallel mask arithmetic processing is performed efficiently by the small-capacity auxiliary memory 302.

87. 发明专利

JPH01255306A DIRECT-CURRENT DIRECT-COUPLED AMPLIFIER CIRCUIT 失效
公开(公告)号：JPH01255306A
公开(公告)日：1989-10-12
申请号：JP8275588
申请日：1988-04-04
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG
发明人： YONETANI HIROYUKI , WATANABE KAZUO
IPC分类号： H03F3/34 , H03F3/347
摘要： PURPOSE:To cancel the offset of the whole in a batch by causing an adjusting current to flow to the input resistance of a first stage amplifier circuit. CONSTITUTION:Into the input of a first stage amplifier circuit A1, resistances R1 and R2 are inserted in series. A voltage comparator circuit VD makes a difference voltage between an output signal V0 of an output stage amplifier circuit An and a reference voltage Vref or the amplified voltage into an offset voltage Vof, an offset canceling control circuit OFC connects a switch circuit SW1 to the resistance R1 side when, for example, the offset voltage Vof is a positive voltage, a switch S1 in a switch circuit SW2 is made into an on- condition, and a constant current I0 made to flow to the resistance R1 is made to flow as an offset canceling current Id. Until the polarity of the offset voltage Vof is inverted, switches S2-Sm are successively made into the on-condition, and the canceling current Id is increased. Thus, the offset of the whole can be automatically canceled in a batch.

88. 发明专利

JPH01243726A ADM PROCESSING CIRCUIT 失效
公开(公告)号：JPH01243726A
公开(公告)日：1989-09-28
申请号：JP6952488
申请日：1988-03-25
申请人： HITACHI LTD , HITACHI TOBU SEMICONDUCTOR LTD
发明人： SHIMAZU KATSUHIRO , WATANABE KAZUO , KOMATSU TATSUYA
IPC分类号： H03M3/04
摘要： PURPOSE:To prevent a predictor from being excessively formed in a silent condition by practically making a PQ arithmetic function invalid when an encoded bit pattern is at a prescribed pattern, and adding a holding function to hold a quantizing width to a preceding value. CONSTITUTION:In a PQ arithmetic circuit, a multiplexer MPX and a holding circuit are added to a P/Q selecting part and a difference holding circuit. In a decoder circuit DCR, when the encoded bit patterns are at 011 and 100, the circuit DCR stops a P/Q selecting action, and sets the multiplexer at a holding side. Thus, the quantizing width of the preceding stage is inputted to an arithmetic circuit ALU. The arithmetic circuit ALU forms the predictor for the encoding from the output of a delay circuit D and the addition and substraction of the quantizing width by means of a PQ operation, and outputs it to a digital comparator COMP.

89. 发明专利

JPS63164617A FREQUENCY DIVISION CIRCUIT 失效
公开(公告)号：JPS63164617A
公开(公告)日：1988-07-08
申请号：JP30849886
申请日：1986-12-26
申请人： HITACHI LTD , HITACHI TOBU SEMICONDUCTOR LTD
发明人： SHIMAZU KATSUHIRO , WATANABE KAZUO
IPC分类号： H03K23/40 , H03K23/00 , H03K23/52 , H03K27/00
摘要： PURPOSE:To decrease number of components of a frequency division circuit possibly by constituting a part corresponding to a holding circuit by a biphase dynamic shift register, connecting plural stages of dynamic shift registers in a form of feedback and applying biphase oscillation to apply frequency division in the clock synchronism. CONSTITUTION:As a frequency division output COUT1 of a 1st stage frequency division circuit FF1, the period of clocks CP1, CP2 is outputted through 1/2 frequency division. Moreover, the frequency division output COUT1 of the FF1 is being frequency-divided by 1/2 each by frequency division circuits FF2, FF3 on the 2nd and succeeding stages. The holding circuit constituting the frequency divider circuit 10 of each stage is constituted by the biphase dynamic shift register in the multi-stage frequency divider circuit 10 and in addition, odd number stages of the biphase dynamic shift registers are connected in a form of feedback and frequency division is applied through biphase oscillation at the clock synchronism. Thus, the circuit inputting the frequency division input or extracting the frequency division output is constituted by having only to use one AND gate G12.

90. 发明专利

JPS6317259B2 失效
公开(公告)号：JPS6317259B2
公开(公告)日：1988-04-13
申请号：JP11171780
申请日：1980-08-15
申请人： HITACHI LTD
发明人： WATANABE KAZUO , IENAKA MASANORI
IPC分类号： H04H1/00 , H04H40/36

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