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1. 发明专利

JPH08307172A VARIABLE GAIN AMPLIFIER 失效
公开(公告)号：JPH08307172A
公开(公告)日：1996-11-22
申请号：JP10659395
申请日：1995-04-28
申请人： HITACHI LTD , ALPS ELECTRIC CO LTD
发明人： ENDO TAKEFUMI , WATANABE KAZUO , OKAZAKI MITSUYA
IPC分类号： H03G3/12 , H03F3/45 , H03G3/10
摘要： PURPOSE: To attain smooth gain control with stable accuracy over a wide gain range by providing a variable gain amplifier circuit and a compensation circuit providing a prescribed temperature characteristic to an operation bias current to cancel the gain temperature characteristic. CONSTITUTION: A differential amplifier circuit A is made up of differential bipolar transistors (TRs) Q9, Q10 of emitter coupling, a bipolar TR Q8 controlling a collector current I, supplied to a common emitter of the TRs Q9, Q10 and collector load resistors Rc 1, Rc 2 interposed in series between collector terminals of the TRs Q9, Q10 and a power supply voltage Vcc. A voltage current conversion circuit B is made up of an operational amplifier 1, a bipolar TRQ1 connected between an output terminal and an inverting input terminal of the operational amplifier 1, a resistor R1, and bias voltage sources 2, 3. Then the voltage current conversion circuit B conducts temperature compensation to keep a gain of the TRQ8 constant with respect to the temperature.

2. 发明专利

JPH08148947A COMMON BASE TRANSISTOR AMPLIFIER 失效
公开(公告)号：JPH08148947A
公开(公告)日：1996-06-07
申请号：JP15623295
申请日：1995-06-22
申请人： ALPS ELECTRIC CO LTD , HITACHI LTD
发明人： OKAZAKI MITSUYA , WATANABE KAZUO , ENDO TAKEFUMI
IPC分类号： H03F1/26 , H03F3/04 , H03F3/19 , H03F3/45
摘要： PURPOSE: To provide a common base transistor amplifier provided with extremely low noise figure(NF) characteristics by almost completely cancelling a noise voltage generated in the transistor of a constant current circuit. CONSTITUTION: This amplifier is provided with a pair of the transistors 1 and 2 whose base is high frequency grounded and collector is connected to a signal output terminal 16, a high frequency transformer 10 provided with a primary winding wire 10p connected to a signal input terminal 15 and a secondary winding wire 10s provided with a middle point tap 10t for which both ends of the secondary winding wire 10s are respectivelly connected to the emitters of the pair of the transistors 1 and 2 and the constant current circuit connected to the middle point tap 10t of the secondary winding wire 10s for making a bias current flow to the transistors 1 and 2. In this case, since the noise voltage generated in the transistor 7 of the constant current circuit is inputted through the secondary winding wire 10s to the emitters of the transistors 1 and 2 by common-mode, the noise voltage does not appear in the signal output terminal 16.

3. 发明专利

JPH07231234A AUTOMATIC GAIN CONTROL AMPLIFIER 失效
公开(公告)号：JPH07231234A
公开(公告)日：1995-08-29
申请号：JP2130294
申请日：1994-02-18
申请人： ALPS ELECTRIC CO LTD , HITACHI LTD
发明人： OKAZAKI MITSUYA , WATANABE KAZUO , ENDO TAKEFUMI
IPC分类号： H03G3/30 , H03F3/45
摘要： PURPOSE:To obtain an automatic gain control amplifier having a wide dynamic range without causing signal distortion even when a large level signal is received. CONSTITUTION:The automatic gain control amplifier is provided with a variable gain amplifier circuit A, a variable attenuation circuit B whose input terminal connects to an input terminal of the variable gain amplifier circuit A, a 1st current control circuit C controlling an operating current I1 of the variable gain amplifier circuit A and a 2nd current control circuit D controlling an operating current I2 of the variable attenuation circuit B. Then the 1st current control circuit C and the 2nd current control circuit D receiving a gain control voltage Vagc to control the increase/decrease in the operating current I1 of the variable gain amplifier circuit A and to control the increase/decrease in the operating current I2 of the variable attenuation circuit B reversely to each other.

4. 发明专利

JP2002214306A SEMICONDUCTOR INTEGRATED CIRCUIT 失效
公开(公告)号：JP2002214306A
公开(公告)日：2002-07-31
申请号：JP2001006558
申请日：2001-01-15
申请人： HITACHI LTD
发明人： OSAWA HIROTAKA , KASAHARA MASUMI , WATANABE KAZUO
IPC分类号： G01R31/316 , G01R31/28 , G01R31/3167 , G01R31/317 , H01L21/822 , H01L21/8249 , H01L27/04 , H01L27/06
摘要： PROBLEM TO BE SOLVED: To prevent the noise generated in a digital part from transmitting to and affecting on an analog circuit through a signal route from the test circuit of the digital part to an analog input and output pin to which the test circuit is connected, in an analog-digital mixed semiconductor integrated circuit, when using a test input and output pin conformed to the test circuit of the digital part also as the general operation input and output pin of the analog part. SOLUTION: The test input and output pin conformed to the test circuit 112 of the digital part is used also as the general operation input and output pin 141 of the analog part. Change-over switches 171 and 172 are provided between the analog pin and the analog circuit and on the signal line 160 from the analog pin to the test circuit of the digital part, respectively. Further, switching elements 173 and 174 for fixing the potential of the signal line to a prescribed potential as grounding potential in general operation are provided on both ends of the signal line between the test circuit of the digital part and the common input and output pin.

5. 发明专利

JP2001044872A SEMICONDUCTOR INTEGRATED CIRCUIT FOR PROCESSING RECEPTION SIGNAL 失效
公开(公告)号：JP2001044872A
公开(公告)日：2001-02-16
申请号：JP22074399
申请日：1999-08-04
申请人： HITACHI LTD
发明人： YOKOTA MASAKATSU , WATANABE KAZUO , PORUKAA PORITTSU , MARKUS FENEBAAGU
IPC分类号： H04B1/26 , H04B1/16 , H04B1/28
摘要： PROBLEM TO BE SOLVED: To reduce the number of parts and to attain miniaturization by means of processing the reception of a plurality of frequency bands in a common circuit by up-converting a low frequency signals to match with a high frequency signal. SOLUTION: When receiving the signal of two frequency band, that is, an L-Band and a VHF band, the signal of the 174-245 MHz VHF band separated by a duplexer 101 is synthesized with the local oscillation signal of 126.992 MHz, which is generated by a PLL circuit 131, by means of a mixer 141 and only a 1443.992-1514.992 MHz convert signal passes through a BPF 122 and is up-converted. Then it is selected by a change-over switch 102, passes through an LNA 112 and the BPF 123, is combined with the local oscillation signal of 1230.992-1301.992 MHz, which is generated by the PLL circuit 132, by means of the second mixer 142 and converted into an intermediate frequency signal of 213 MHz. Then a disturbance wave is removed by a band-pass filter 124, combined with the local oscillation signal of 215 MHz from the PLL circuit 133, converted into a signal of 2 MHz and outputted to a demodulating circuit.

6. 发明专利

JPH11355138A PLL CIRCUIT AND RADIO COMMUNICATION TERMINAL EQUIPMENT USING THE SAME 失效
公开(公告)号：JPH11355138A
公开(公告)日：1999-12-24
申请号：JP16178698
申请日：1998-06-10
申请人： HITACHI LTD
发明人： HORI KAZUAKI , KOKUBO MASARU , WATANABE KAZUO
IPC分类号： H03L7/16 , H03L7/185 , H04B1/3822 , H04B1/40
摘要： PROBLEM TO BE SOLVED: To reduce systems of an RF-local VCO and a means for stabilizing its frequency to be one system in a dual band transmission system. SOLUTION: A second mixer 3 is inserted between a phase comparator 1 and a mixer 2 for executing frequency-conversion (down conversion) by an RF-local frequency fLO1 which in linked with a desired transmission frequency. Moreover, it is converted into a final comparison frequency fREF1 by the second mixer 3 so as to constitute a PLL loop. A second local signal generator 8 is disposed as a local signal source to the second mixer 3. Thus, the RF-local signal generator for selecting a transmission frequency is made to be one system and the local signal frequency of the second mixer 3 is combined so that a transmission frequency band is selected.

7. 发明专利

JPH08149003A PLL FREQUENCY SYNTHESIZER AND DEVICE USING THE SYNTHESIZER 失效
公开(公告)号：JPH08149003A
公开(公告)日：1996-06-07
申请号：JP28520494
申请日：1994-11-18
申请人： HITACHI LTD
发明人： MATSUI HIROAKI , KATAGISHI MAKOTO , AKITAKE ISAO , WATANABE KAZUO , HAGITANI SHINICHI
IPC分类号： H03L7/183
摘要： PURPOSE: To provide a PLL frequency synthesizer which can shorten the waiting time needed for setting a dividing ratio and also can quickly set the dividing ratio. CONSTITUTION: The input signal received from an input terminal 2 and the reference signal received from an input terminal 6 are divided by a counter 8 and a reference counter 9 respectively. The output signals of both counters 8 and 9 are compared with each other by a phase comparator 10, and this comparison output is supplied to an output terminal 13 or to an output terminal 12 via a switch 11. If the setting data are inputted from an input terminal 3 while an LE (load enable) signal is kept at 'L', the setting data are fetched by a shift register 7. Then the LE signal is changed to 'H' and a latch clock is outputted from a latch clock generating circuit 15 at the rise of the LE signal. Thus the setting data are transferred to the counters 8 or 9 from the register 7, and the dividing ratios of both counters are changed. The switch 11 is turned on and the terminal 12 is effective while the LE signal is kept at 'H'.

8. 发明专利

JPH08135998A AIR CONDITIONER 失效
公开(公告)号：JPH08135998A
公开(公告)日：1996-05-31
申请号：JP27879094
申请日：1994-11-14
申请人： HITACHI LTD
发明人： WATANABE KAZUO
IPC分类号： F24F13/20 , F24F1/00
摘要： PURPOSE: To enhance the efficiency and to simplify an air conditioner by applying a structure in which indoor electric components are disposed on the back surface of an indoor unit chassis or between the front surface of an indoor heat exchanger and a decorative cover. CONSTITUTION: Indoor electric components 6 are disposed on the back surface of an indoor unit chassis 1 or between the front surface of an indoor heat exchanger 2 and a decorative cover 7, thereby enhancing the efficiency and simplifying an air conditioner.

9. 发明专利

JPH01255321A WAVEFORM ENCODING CIRCUIT 失效
公开(公告)号：JPH01255321A
公开(公告)日：1989-10-12
申请号：JP8369888
申请日：1988-04-05
申请人： HITACHI LTD , HITACHI TOBU SEMICONDUCTOR LTD
发明人： SHIMAZU KATSUHIRO , WATANABE KAZUO
IPC分类号： H03M3/04
摘要： PURPOSE:To maintain a high sound quality, and simultaneously, to execute a substantial data compression by increasing a sampling frequency when a sound exists, and simultaneously, switching the sampling frequency, when the sound does not exist, to a low frequency. CONSTITUTION:An analog sound signal Vin is converted to a digital input signal Din by a sampling clock Fs1 of the frequency six-fold or above that of the cut-off frequency of a low-pass filter LPF1 in an analog/digital converting circuit ADC, and a signal encoded by a digital comparator COMP is made into a bit string signal by a delay group composed of a shift register RG1. When a carrier detection CD detects the fact that the sound does not exist in the bit string of the shift register RG1 two times or above, a changeover signal C2 is supplied to a sampling clock generating circuit SCG, and the sampling clock fs1 is switched to a sampling clock fs2 of the lower frequency. Thus, the high sound quality is maintained, and simultaneously, the substantial data compression can be executed.

10. 发明专利

JPH01106606A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPH01106606A
公开(公告)日：1989-04-24
申请号：JP26454087
申请日：1987-10-20
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG
发明人： YONETANI HIROYUKI , WATANABE KAZUO
IPC分类号： G11C11/417 , G11C11/34 , G11C11/409 , H03F3/34 , H03F3/345 , H03K5/02
摘要： PURPOSE:To stabilize the circuit and to attain low power consumption of the title device by making an output signal level constant depending on the on-state of a switch MOSFET when the operating current of the amplifier circuit is interrupted. CONSTITUTION:An N-channel switch MOSFET Q8 is provided between a gate and a drain of the gate of the MOSFET Q4. A control signal STB is supplied to the gate of the FET Q8. Thus, the FET Q8 is turned on in the standby mode where a control signal STB goes to a high level so as to fix a node N2 to a potential such as VCC-Vth equal to the potential of the node N1. Since the voltage VCC-Vth reaches a level higher than a logic threshold voltage of a CMOS inverter circuit, the level conversion output in the standby mode is fixed to a low level.

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