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    • 2. 发明专利
    • FREQUENCY DIVISION CIRCUIT
    • JPS63164617A
    • 1988-07-08
    • JP30849886
    • 1986-12-26
    • HITACHI LTDHITACHI TOBU SEMICONDUCTOR LTD
    • SHIMAZU KATSUHIROWATANABE KAZUO
    • H03K23/40H03K23/00H03K23/52H03K27/00
    • PURPOSE:To decrease number of components of a frequency division circuit possibly by constituting a part corresponding to a holding circuit by a biphase dynamic shift register, connecting plural stages of dynamic shift registers in a form of feedback and applying biphase oscillation to apply frequency division in the clock synchronism. CONSTITUTION:As a frequency division output COUT1 of a 1st stage frequency division circuit FF1, the period of clocks CP1, CP2 is outputted through 1/2 frequency division. Moreover, the frequency division output COUT1 of the FF1 is being frequency-divided by 1/2 each by frequency division circuits FF2, FF3 on the 2nd and succeeding stages. The holding circuit constituting the frequency divider circuit 10 of each stage is constituted by the biphase dynamic shift register in the multi-stage frequency divider circuit 10 and in addition, odd number stages of the biphase dynamic shift registers are connected in a form of feedback and frequency division is applied through biphase oscillation at the clock synchronism. Thus, the circuit inputting the frequency division input or extracting the frequency division output is constituted by having only to use one AND gate G12.
    • 3. 发明专利
    • MULTIPLIER CIRCUIT
    • JPS62154029A
    • 1987-07-09
    • JP29264285
    • 1985-12-27
    • HITACHI TOBU SEMICONDUCTOR LTDHITACHI LTD
    • SHIMAZU KATSUHIROWATANABE KAZUO
    • G06F7/533G06F7/52G06F7/53
    • PURPOSE:To simplify the constitution of a logic circuit obtained a partial product and to speed up remarkably its action by taking a complement of '1' by the algorithm of a booth obtaining a partial product and adding '1' by a Wallence addition tree where a command taking a complement of '2' is given. CONSTITUTION:Logic operation circuits 2A-2D are constituted so as to take a '1' complement of a multiplicand X if the command taking a '2' complement of the multiplicand X is issued from decoders 1A-1D. If the command taking a '2' complement of the multiplicand X is issued from the decoders 1A-1D, it is directly inputted to an adder circuit 3 as addition data adding one to a complement '1' of the multiplicand X. When a signal C1 becomes active, the corresponding logic operation circuits 2A-2D take the complement of '1' of the multiplicand X, and simultaneously the adder circuit 3 adds outputs (AX', BX', CX' and DX') from the logic operation circuits 2A-2D according to the Wallence tree system. The adder circuit 3 adds one to the output where the signal C1 becomes active.
    • 5. 发明专利
    • WAVEFORM ENCODING CIRCUIT
    • JPH01255321A
    • 1989-10-12
    • JP8369888
    • 1988-04-05
    • HITACHI LTDHITACHI TOBU SEMICONDUCTOR LTD
    • SHIMAZU KATSUHIROWATANABE KAZUO
    • H03M3/04
    • PURPOSE:To maintain a high sound quality, and simultaneously, to execute a substantial data compression by increasing a sampling frequency when a sound exists, and simultaneously, switching the sampling frequency, when the sound does not exist, to a low frequency. CONSTITUTION:An analog sound signal Vin is converted to a digital input signal Din by a sampling clock Fs1 of the frequency six-fold or above that of the cut-off frequency of a low-pass filter LPF1 in an analog/digital converting circuit ADC, and a signal encoded by a digital comparator COMP is made into a bit string signal by a delay group composed of a shift register RG1. When a carrier detection CD detects the fact that the sound does not exist in the bit string of the shift register RG1 two times or above, a changeover signal C2 is supplied to a sampling clock generating circuit SCG, and the sampling clock fs1 is switched to a sampling clock fs2 of the lower frequency. Thus, the high sound quality is maintained, and simultaneously, the substantial data compression can be executed.