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61. 发明专利

JPH034561A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPH034561A
公开(公告)日：1991-01-10
申请号：JP13946089
申请日：1989-05-31
申请人： HITACHI LTD
发明人： OWADA NOBUO , AKIMORI HIROYUKI , NITTA TAKEHISA , KOBAYASHI TORU , SASABE SHUNJI , KAWAJI MOTONORI , KASAHARA OSAMU
IPC分类号： H01L21/3205 , G06F17/50 , G11C11/401 , H01L21/82 , H01L23/52 , H01L27/118
摘要： PURPOSE:To shorten the production time of a circuit device of this design by a method wherein signal wirings of an X direction are increased in number at a third wiring taking advantage of spaces between basic cells and the surfaces of the basic cells and other signal wirings of a Y direction are increased in number at a second wiring, whereby a circuit is enhanced in mounting rate. CONSTITUTION:A first signal wiring 38 is formed on a logic LSI semiconductor wafer on which basic cells have been arranged using a formed semiconductor manufacturing mask, and then an interlaminar insulating film 39, a connection hole 40, a second signal wire 41, an interlaminar insulating film 42, a connection hole 43, a third signal wiring 44, an interlaminar insulating film 45, a fourth signal wiring 46, and a passivation film 47 are successively formed to constitute a logic LSI. On the other hand, signal wirings of an X direction are increased in number at the third signal wiring 44 by making the wirings small in pitch basing on the X direction wiring information of an X-Y grating wiring channel region, and furthermore the second signal wiring 41 of a Y direction is increased in arrangement number.

62. 发明专利

JPH0247539B2 失效
公开(公告)号：JPH0247539B2
公开(公告)日：1990-10-22
申请号：JP24384483
申请日：1983-12-26
申请人： HITACHI LTD
发明人： SAKATA MASAO , KOBAYASHI HIDE , KASAHARA OSAMU , OOGISHI HIDEJI , ABE KATSUO
IPC分类号： C23C14/36 , C23C14/35 , H01J37/34

63. 发明专利

JPH01262628A DEVICE FOR FORMING THIN-FILM 失效
公开(公告)号：JPH01262628A
公开(公告)日：1989-10-19
申请号：JP9234988
申请日：1988-04-14
申请人： HITACHI LTD
发明人： TAMAOKI MASUKAZU , KASAHARA OSAMU
IPC分类号： C23C14/56 , H01L21/205 , H01L21/31
摘要： PURPOSE:To prevent the formation of a natural oxide film on the surface of an article to be treated positively by surely removing air, etc., staying among the articles to be treated by an inert gas blown off from a gas feeder installed near an opening section in a treating chamber. CONSTITUTION:Articles to be carried 10 such as semiconductor wafers, on which aimed thin-films must be formed, are mounted to a carrier jig 9 on a carrier base 8. The carrier base 8 is lifted while an inert gas 12 is ejected from a plurality of blow-off holes 11a of a gas feeder 11, thus starting carrying-in to a treating chamber 1 of a plurality of the articles to be treated 10. The inert gas 12 is sprayed against the articles to be treated 10 passing through the feeder 11 from the whole circumference prior to the carrying-in to the inside, air staying in the clearances of the articles to be treated 10 held to the jig 9 is removed positively, and carrying-in to the treating chamber 1 together with the articles to be treated 10 is prevented. Accordingly, the formation of natural oxide films prior to the formation of aimed thin-films onto the surfaces of the articles to be treated 10 carried into the treating chamber 1 heated at a fixed temperature is surely obviated.

64. 发明专利

JPS62298168A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS62298168A
公开(公告)日：1987-12-25
申请号：JP14006686
申请日：1986-06-18
申请人： HITACHI LTD
发明人： TAKAHASHI TAKAHIKO , KASAHARA OSAMU , TANEOKA TADAYUKI
IPC分类号： H01L29/43 , H01L21/28
摘要： PURPOSE:To prevent deposition of an Si single crystal at the time of heat treatment and to prevent the increase in electric resistance, by providing a silicon nitride film between an electrode comprising Al, or metal, whose main component is Al, and an active region. CONSTITUTION:In a P-type Si substrate 1, a source 2 and a drain 3, which are two N-type active regions, are separately formed. An insulating film 4 comprising SiO2 is deposited thereon. Opening parts 6 and 6a are formed at places on the source 2 and the drain 3 in the insulating film 4. Ohmic electrodes 7 and 7a are formed through silicon nitride films 8 and 8a. The electrodes 7 and 7a are formed with Al or metal, whose main component is Al. A gate electrode 5 is also formed on the insulating film 4. Even if high temperature heat history is received, an Si single crystal is not deposited between the electrode and the substrate, and the increase in electric resistance can be prevented.

65. 发明专利

JPS60183738A FORMATION OF WIRING 失效
公开(公告)号：JPS60183738A
公开(公告)日：1985-09-19
申请号：JP3851884
申请日：1984-03-02
申请人： HITACHI LTD
发明人： KASAHARA OSAMU
IPC分类号： H01L21/3213 , H01L21/88
摘要： PURPOSE:To improve the yield by a method in which conductive metal films are formed to be adhered on a substrate provided with patterns of non-wiring sections, the whole surface thereof is coated with a mask member and etch-packed, and the conductive metal films are etched away. CONSTITUTION:Patterns of non-wiring sections 3 are formed on a substrate 1 applied with an insulation film 2. Al alloy films 5 are formed to be adhered on the non-wire section patterns 3 and on the substrate. A mask member 6 is then applied thereon, and wholly etched so as to expose the Al alloy films 5a. The Al alloy films 5a are then etched by a wet etching method, If the non-wiring section patterns 3 are composed of an insulative material while the mask member 6 is also insulative, the mask material 6 may be used as an interlaminar insulative material instead of removing and applied to multiplayer wiring. If both of the non-wiring section patterns 3 and the mask member 6 are photoresist, they are etched by O2 plasma etching to form wiring patterns with an Al alloy film 5b. In such a manner, it is prevented that scraps of fragments of conductive metal film or metal film are adhered to conductive metal films of wiring pattarns, and accordingly short-circuit can be prevented.

66. 发明专利

JPS60128696A METHOD OF PRODUCING MULTILAYER WIRING MEMBER 失效
公开(公告)号：JPS60128696A
公开(公告)日：1985-07-09
申请号：JP23614583
申请日：1983-12-16
申请人： HITACHI LTD
发明人： MITANI SHINICHIROU , KASAHARA OSAMU
IPC分类号： H05K3/46

67. 发明专利

JPS59208068A Film forming device 失效
标题翻译：电影制作装置
公开(公告)号：JPS59208068A
公开(公告)日：1984-11-26
申请号：JP8273483
申请日：1983-05-13
申请人： Hitachi Ltd , Hitachi Micro Comput Eng Ltd
发明人： KASAHARA OSAMU , TAKAHASHI SUU
IPC分类号： C23C14/24 , C23C14/34 , H01L21/203 , H01L21/285
CPC分类号： C23C14/24
摘要： PURPOSE:To improve covering performance in the stepped part of a base layer and to realize lift-off by disposing guides between wafers and a film material source for generating film particles. CONSTITUTION:The inside of a bell jar 11 is set at a prescribed degree of vacuum and the inside as well as wafers 14 and, for example, Al 15 on an evaporating tray 17 are heated by a heating means 18. Then the particles of the Al 15 scatter toward four ways in the bell-jar 11 with a scattering source 16 as a center. A part of the particles arrives at the surface of the wafers 14 and forms an Al film thereon. Guide cylinders 19 are disposed between the wafers and the source, the Al particles arrive at the wafers 14 only from the perpendicular direction thereof. Therefore if the wafers 14 are moved relatively with the cylinders 19 by operating a wafer supporting part 13, the films deposited with the Al respectively in the perpendicular direction are formed over the entire surface of the wafers 14.
摘要翻译：目的：提高基层阶梯部分的覆盖性能，并通过在晶片和薄膜材料源之间设置引导件来实现剥离，从而产生膜颗粒。构成：钟罩11的内部被设定在规定的真空度，并且内部以及蒸发托盘17上的晶片14和例如Al 15被加热装置18加热。然后， Al 15以喇叭口11以散射光源16为中心向四个方向散射。一部分颗粒到达晶片14的表面并在其上形成Al膜。引导圆筒19设置在晶片和源之间，Al颗粒仅从其垂直方向到达晶片14。因此，如果晶片14通过操作晶片支撑部分13而相对于气缸19移动，则在晶片14的整个表面上形成分别垂直方向沉积的Al的膜。

68. 发明专利

JPS5780739A Semiconductor integrated circuit device and manufacture thereof 失效
标题翻译：半导体集成电路器件及其制造
公开(公告)号：JPS5780739A
公开(公告)日：1982-05-20
申请号：JP15594580
申请日：1980-11-07
申请人： Hitachi Ltd
发明人： KASAHARA OSAMU , SHIMIZU SHINJI , MIYAZAWA HIROYUKI , NAKADA KENSUKE
IPC分类号： H01L29/78 , H01L21/3205 , H01L23/52 , H01L23/532 , H01L27/108
CPC分类号： H01L27/10805 , H01L23/53257 , H01L23/53271 , H01L2924/0002 , H01L2924/00
摘要： PURPOSE:To obtain a wire which can match by itself and has small specific resistance and fast signal transmission speed with heat resistance for an IC by forming in 3-layer structure of high melting point metal-metal containing polysilicon-Si. CONSTITUTION:A gate electrode of 3-layer structure is formed on the gate oxidized film 53 of a P type Si substrate 51, N type layers 572, 573 matched by itself are provided, the 3-layer structure electrode is attached to the layer 572, and an aluminum layer is attached to the N type layer 573. To form the electrode of 3-layer structure, CVD polysilicons 541, 542 are formed, phosphorus is added, Mos 551, 552 containing 10wt% of Si are commonly deposited and laminated, pure Mos 561, 562 are sputtered and laminated, are then plasma etched to form the electrode of 3-layer, the electrode is then annealed in N2, and Si is uniformly distributed in the Mo layer. According to this structure, the three layers are bonded to each other, with the result that the specific resistance becomes vary small value such as 30-35muOMEGAcm. Further, the Mo containing Si prevents an impurity to be mixed at the depositing time from being stopped by the polysilicon and not to be diffused in a semiconductor substrate. In this manner, a semiconductor integrated circuit device having small specific resistance and short transmission time can be obtained.
摘要翻译：目的：通过在含有多晶硅的高熔点金属 - 金属的3层结构中形成，获得能够自己匹配的电线，具有小的电阻率和具有耐热性的IC的耐热性的快速信号传输速度。构成：在P型Si衬底51的栅极氧化膜53上形成3层结构的栅电极，设置与其自身匹配的N +型层572,573，将3层结构电极附着于层572和铝层附着到N +型层573.为了形成3层结构的电极，形成CVD多晶硅541,542，加入磷，含有10重量％的氧化物的Mos 551,552 通常沉积和层压Si，纯Mos 561,562被溅射和层压，然后进行等离子体蚀刻以形成3层电极，然后将电极在N 2中退火，并且Si均匀地分布在Mo层中。根据该结构，三层结合，结果电阻率变小，例如30-35μmOMEGAcm。此外，含Mo的Si防止杂质在沉积时间被多晶硅停止而不被扩散到半导体衬底中。以这种方式，可以获得具有小电阻和短的传输时间的半导体集成电路器件。

69. 发明专利

JPS56124246A MANUFACTURING OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS56124246A
公开(公告)日：1981-09-29
申请号：JP2430381
申请日：1981-02-23
申请人： HITACHI LTD
发明人： KASAHARA OSAMU , MASUOKA KIYOTAKE
IPC分类号： H01L21/60 , H01L21/28 , H01L23/532 , H01L29/43
摘要： PURPOSE:To improve joining strength of a substrate onto a pad, by providing a joining pad directly on an SiO2 membrane by using a wiring material. CONSTITUTION:A base emitter layer is formed on an Si substrate 1. As for the emitter layer, the SiO2 membrane 4 is provided with an opening, Pt is attached by soldering to selectively form Pt-Si layer 6, and a 2-layer wiring for Mo 7 and Al 8 is provided. By covering with SiO2 10 and selectively providing openings 11 and 10a, an Al second wiring 12a and a pad 12a are provided. As the Al pad is strongly joined to the SiO2 membrane 4, it can be prevented from exfoliation at the time of supersonic joining, and this becomes furthermore effective when a thermal oxide membrane is used in particular. In this mechanism, possibility of exfoliation can be reduced to approximately 1% of that of a conventional Al-Mo dual structure.

70. 发明专利

JPS52156476A STRUCTURE FOR HOLDING MEMBER 失效
公开(公告)号：JPS52156476A
公开(公告)日：1977-12-26
申请号：JP7314476
申请日：1976-06-23
申请人： HITACHI LTD
发明人： YOSHIDA MAKOTO , OOMAE MINE , KASAHARA OSAMU
IPC分类号： B23P21/00 , B23P19/00 , H01L21/677 , H01L21/68 , H01L23/00 , H01L23/32
摘要： PURPOSE:To automatically and certainly hold a stem contained in a jig and to feed the stem to a welding jig in a structure for holding members used in assembly of a can-seal type transistor.

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