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51. 发明专利

JPH0697370A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND LAYOUT AND ROUTING THEREFOR 失效
公开(公告)号：JPH0697370A
公开(公告)日：1994-04-08
申请号：JP5166293
申请日：1993-03-12
申请人： HITACHI LTD
发明人： MOCHIDA TETSUYA , SHINOZAKI MASATSUGU , KATSUBE TAKEKI , ISHIKAWA SUKETAKA , OSAKA HIDEKI , FUKUNAKA HIDETADA , MIURA SHUICHI
IPC分类号： H01L21/82 , H01L21/822 , H01L27/04
摘要： PURPOSE:To shorten the route in an LSI by routing different buses while collecting the corresponding bites or bits in same data path block or splitting into unit bites. CONSTITUTION:A semiconductor integrated circuit 101 controls connection of buses A102, B103 where bus signals 117-0, 116-0, 117-1, 116-1 have corresponding bites. Bus signal of 0 bite represented by group No. 0 is connected with a data path block 105-0 for group 0. Corresponding bites are alotted each other by assigning same group numbers to same bites. Data path blocks 105-0, 105-1, etc., are arranged on the periphery of semiconductor substrate thus shortening the signal line of data path in an LSI.

52. 发明专利

JPH0689255A COMPUTER SYSTEM AND HIGH-SPEED I/O DATA TRANSFER METHOD 失效
公开(公告)号：JPH0689255A
公开(公告)日：1994-03-29
申请号：JP23846592
申请日：1992-09-07
申请人： HITACHI LTD
发明人： MORIOKA MICHIO , KUROSAWA KENICHI , KOGA KAZUYOSHI , ISHIKAWA SUKETAKA
IPC分类号： G06F13/12
摘要： PURPOSE:To directly transfer a large size of block data in a cache memory to an I/O device by an instruction which a processor executes. CONSTITUTION:A block transfer instruction for forcibly writing block data in the cache memory in a main memory and I/O space is provide and, moreover, an interface unit 200 which connects the processor, the main memory and the I/O device, is provided with a means 2010 for identifying a transaction by the block transfer instruction. Then, in accordance with the result of the identifying means 2010, the received transaction is stored in both main memory transmission buffers 2060, 2070 and I/O device transmission buffers 2090, 2100 and the address of the transaction is converted into the address for the I/O device by address conversion mechanism 2110.

53. 发明专利

JPH0689196A COMPUTER SYSTEM AND MAIN MEMORY CONTROLLER 失效
公开(公告)号：JPH0689196A
公开(公告)日：1994-03-29
申请号：JP23846492
申请日：1992-09-07
申请人： HITACHI LTD
发明人： KUROSAWA KENICHI , MORIOKA MICHIO , ISHIKAWA SUKETAKA , FUKUNAKA HIDETADA , NAKAYAMA HARUYUKI , IWAMOTO HIROSHI
IPC分类号： G06F9/46 , G06F11/00 , G06F11/10 , G06F11/14
摘要： PURPOSE:To avoid the system down regardless of the occurrence of a memory system fault with respect to the memory of a computer to which an error correction code is added. CONSTITUTION:If an error is detected by an error report signal C40 (C70), an error charging circuit D10 selects data A150 and A170 with a specific error correction code by selectors A140 and A160 instead of write data C100 (C110) to the memory transferred from a processor and sends these selected data to a memory bus B110 to write them in the memory. When data read from the memory is inputted from the memory bus B110, a charged error detecting circuit 020 detects whether this data is data A150 and A170 with the specific error correction code or not. When data with the specific error correction code is read out, the charged error detecting circuit D20 stops execution of only software which performed this read.

54. 发明专利

JPH0627200A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPH0627200A
公开(公告)日：1994-02-04
申请号：JP18016192
申请日：1992-07-08
申请人： HITACHI LTD
发明人： MORIKAWA TAKUJI , MOCHIDA TETSUYA , ISHIKAWA SUKETAKA
IPC分类号： G01R31/28 , H01L21/66 , H01L21/822 , H01L27/04
摘要： PURPOSE:To provide a semiconductor IC unit which allows a scan circuit generated for diagnosing LSI single unit to be utilized with a scan interface mounted on a base board as a different interface. CONSTITUTION:A semiconductor IC unit 1 integrated of transistor circuits for configuring a flip flop on a semiconductor base board consists of an interface conversion circuit 2 (conversion means), selector 3, a normal operation circuit 4, an LSI single unit diagnosis scan control circuit 5 (scan control means), a flip flap 6, etc. An normal operation mode or LSI single unit diagnosis operation mode is selected by an normal operation/LSI single unit diagnosis common pin 8 (scan means) and a mode signal pin 9, and at the time of on-board scan in normal operation, the signal inputted from an on-board scan signal interface 7 is converted into the data for the LSI single unit diagnosis scan control circuit 5 by the inter-face conversion circuit 2.

55. 发明专利

JPH04364096A COOLER 失效
公开(公告)号：JPH04364096A
公开(公告)日：1992-12-16
申请号：JP13875191
申请日：1991-06-11
申请人： HITACHI LTD , HITACHI COMPUTER ELECTRONIC
发明人： MIYAZAKI HIROYASU , KOMIYA MITSUO , ISHIKAWA SUKETAKA
IPC分类号： G06F1/20 , H05K7/20
摘要： PURPOSE:To conduct the temperature stabilization of a semiconductor device in its early stages by controlling a liquid circulating pump and a liquid air heat exchanger so that the liquid temperature may rise quickly to a certain temperature at start-up of an electronic circuit device, receiving the temperature information from a temperature monitor. CONSTITUTION:A microprocessor 9 monitors the liquid temperature of a liquid circulating cooling system in every fixed time by a temperature monitor 8. In case, the liquid temperature is low, it sends out a signal to a cooling controller 10 so that it may weaken the cooling capacities of a liquid pump 3 and the blower 5 of a liquid-air heat exchanger so as to raise the liquid temperature. This liquid temperature rises by the heating from the heating part of a printed board 1. And when the liquid temperature reaches a certain value, the microprocessor 9 sends out a signal to the cooling controller 10 so that it may maintain the liquid temperature at a certain temperature. Hereby, the cooling capacities of the liquid circulation pump 3 and the blower of the liquid-air heat exchanger is maintained constant.

56. 发明专利

JPH03268011A CLOCK SIGNAL SUPPLY DEVICE 失效
公开(公告)号：JPH03268011A
公开(公告)日：1991-11-28
申请号：JP6702490
申请日：1990-03-19
申请人： HITACHI LTD
发明人： KUMAGAI TAKASHI , ISHIKAWA SUKETAKA , KAWASHIMA SEIICHI , FUJITA BUNICHI
IPC分类号： G06F1/10
摘要： PURPOSE:To make a clock skew small in a system of a slave clock supply device independently from a clock skew of the whole device by dividing the clock supply into a master clock supply device and a slave clock supply device, and generating a reference signal by the slave clock supply device. CONSTITUTION:In a master clock supply device 151, only a clock signal and a synchronizing signal are generated. In a slave clock supply device 152, the clock signal and the synchronizing signal from the master clock supply device 151 are received, and in a frequency-dividing circuit 106 in the slave clock supply device 152, the clock signal is frequency-divided, and a reference signal is formed. In such a way, since the reference signal is generated by the slave clock supply device 152, a clock skew can be made small in a system 11 of the slave clock supply device 152, and the device is not influenced by the clock skew of the whole device.

57. 发明专利

JPS6226723B2 失效
公开(公告)号：JPS6226723B2
公开(公告)日：1987-06-10
申请号：JP1162682
申请日：1982-01-29
申请人： HITACHI LTD
发明人： FUKUDA MASAHARU , OOSHIMA YOSHIO , ISHIKAWA SUKETAKA , OOTSUKI TOORU
IPC分类号： G06F7/53 , G06F7/491 , G06F7/496 , G06F7/508 , G06F7/52 , G06F7/527

58. 发明专利

JPS6273337A SCAN-IN AND SCAN-OUT SYSTEM FOR INTEGRATED CIRCUIT 失效
公开(公告)号：JPS6273337A
公开(公告)日：1987-04-04
申请号：JP21230685
申请日：1985-09-27
申请人： HITACHI LTD
发明人： ISHII YASUHIRO , IMAI YASUHIRO , ISHIKAWA SUKETAKA
IPC分类号： G06F11/22 , G01R31/28
摘要： PURPOSE:To simplify the scan in and scan out operation of FF groups to shorten the scan time by providing a scan clock distributing circuit to allocate scan data to an optional integrated circuit. CONSTITUTION:A scan clock distributing circuit 100 and scan logic incorporating integrated circuits 101-103 are provided, and circuits 101 and 103 scan in and out FFs 140-142 by their scan logics. When an external signal SE goes to the high level after counters in the circuit 100 and FFs are initialized, a scan clock signal corresponding to the data part of a signal SID is divided into three, and bits 0-2 are assigned to signals 100 and 120, and bits 3-5 are assigned to signals 111 and 121, and bits 6-8 are assigned to signals 112 and 122. FFs in each integrated circuit have the same scan address, and scan clocks SIT1 and SIT2 to 9-bit scan data are distributed to individual integrated circuits to scan in/out FF groups 140-142 all at once.

59. 发明专利

JPS6142302B2 失效
公开(公告)号：JPS6142302B2
公开(公告)日：1986-09-20
申请号：JP3524282
申请日：1982-03-08
申请人： HITACHI LTD
发明人： ISHIKAWA SUKETAKA
IPC分类号： G06F12/10 , G06F12/08 , G06F13/00

60. 发明专利

JPS6148036A Processing unit 失效
标题翻译：处理单元
公开(公告)号：JPS6148036A
公开(公告)日：1986-03-08
申请号：JP16931884
申请日：1984-08-15
申请人： Hitachi Ltd
发明人： SAKAI TATSUYA , ISHIKAWA SUKETAKA
IPC分类号： G06F7/38 , G06F7/00 , G06F7/483 , G06F7/491 , G06F7/493 , G06F7/494 , G06F7/50 , G06F7/76
CPC分类号： G06F7/494 , G06F7/4991 , G06F2207/3828 , G06F2207/4924
摘要： PURPOSE:To obtain a high-speed N-ary operation overflow detecting means by detecting an overflow in the case where an effective data included in an N-ary operation result is larger than a result storing region in accordance with an effective data most significant position indicating value obtained from the N-ary operation and a value showing the length of the result storing region. CONSTITUTION:An overflow decision circuit 13 carries out a logical operation of OVF=OV0+OV1+CAR.(S1+S2+A). Herein, (S1+S2+A) indicates a conditional expression showing that a decimal adder carries out addition between the same code data. CAR.(S1+S2+A) shows that when the addition between the same code data is performed, there is a carry CAR from a top bit of a binary adder. When any one of first and second operands exceeds 8 byte, initially, the operation of the latter half of 8 byte is carried out. At that time, CAR is not given to the overflow decision circuit 13 but used during the addition of the other byte carried out in the next place through a bus fed to a least significant bit of the binary adder 2.
摘要翻译：目的：通过在N运算结果中包含的有效数据大于根据有效数据最高有效位置的结果存储区域的情况下检测溢出来获得高速N运算溢出检测装置指示从N运算操作获得的值和表示结果存储区域的长度的值。构成：溢出判定电路13执行OVF = OV0 + OV1 + CAR（S1 + S2 + A）的逻辑运算。这里，（S1 + S2 + A）表示表示十进位加法器在相同代码数据之间执行加法的条件表达式。 CAR（S1 + S2 + A）表示当执行相同代码数据之间的相加时，存在来自二进制加法器的顶部位的进位CAR。当第一和第二操作数中的任何一个超过8字节时，最初执行8字节后半部分的操作。此时，不向溢出判定电路13给出CAR，而是在通过馈送到二进制加法器2的最低有效位的总线的下一次执行的另一字节的加法期间使用CAR。

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