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1. 发明专利

JPH0863443A DATA TRANSFER METHOD AND MUTUAL CONNECTING SWITCH DEVICE 失效
公开(公告)号：JPH0863443A
公开(公告)日：1996-03-08
申请号：JP19391594
申请日：1994-08-18
申请人： HITACHI LTD
发明人： MURASE SHOICHI , NAKAYAMA HARUYUKI , AIMOTO TAKESHI
IPC分类号： G06F15/16 , G06F13/362 , G06F15/163 , G06F15/177
摘要： PURPOSE: To avoid a deadlock state when plural one-to-multiple requests are made at a time and to perform a fast one-to-multiple communication. CONSTITUTION: Switch setting right is obtained first (1). Then all-node access right is obtained next (S2). After the switch setting right is released (S3), data transfer is performed (S4) and then the all-node access right is released (S5). Thus, if a transmission destination conflict is caused when plural one-to-multiple communication are made at the same time, data transfer is serialized and performed, so the deadlock state can be avoided. When there is no transmission destination conflict, the data transfer is performed substantially in parallel, so the wait time can greatly be shortened.

2. 发明专利

JPH02257733A LOOP TRANSMISSION SYSTEM 失效
公开(公告)号：JPH02257733A
公开(公告)日：1990-10-18
申请号：JP7666289
申请日：1989-03-30
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG
发明人： NAKAMURA KAZUNORI , SUKEGAWA FUMIO , NAKAYAMA HARUYUKI
IPC分类号： H04L12/42
摘要： PURPOSE:To eliminate the need for the limit of node number due to alignment jitter by devising a system such that the number of node equipments pulling-in a data from a same system in a closed loop by loopback connection does not exceed continuously a prescribed number (n) determined in advance. CONSTITUTION:The system is provided with a reception section 10 receiving a signal from active and reserve system transmission lines, a transmission section 12 sending a signal to the transmission line of the active and reserve system, a control section 13, a SW section 11 applying the selection control of a data and a clock based on an instruction from the control section 13 and an oscillator 14 for internal clock. Plural node equipments 1-6 are connected to the active and reserve system loop transmission lines. Then the system is so devised that the number of node equipments pulling-in the data from a same system does not exceed continuously the prescribed number (n) determined in advance, in a closed loop formed by a loopback connection. Thus, the limit of the node number by alignment jitter is eliminated.

3. 发明专利

JPH06314239A PROCESSOR SYSTEM 失效
公开(公告)号：JPH06314239A
公开(公告)日：1994-11-08
申请号：JP10219793
申请日：1993-04-28
申请人： HITACHI LTD
发明人： NAKAYAMA HARUYUKI
IPC分类号： G06F12/08
摘要： PURPOSE:To provide a system whose performance does not depend upon the number of processors or memory capacity. CONSTITUTION:In the system provided with the processors 11/12 provided with a cache memory 14, two or more storage devices 16 to 19, and nodes 1 to 9, the nodes 2/3 send a read-out instruction to a transmission line at the time of reading out information, and each corresponding node 4 to 7 sends the information stored in the storage device to the transmission line when it receives the read-out instruction, and each node 2/3 stores the read out information in a cache memory, and when another node sends the read-out instruction to a corresponding address, it sends the information stored in the cache memory corresponding to the address to the node having issued the read-out instruction.

4. 发明专利

JPH04211545A CONTROL INFORMATION TRANSMISSION SYSTEM FOR RING LAN SYSTEM 失效
公开(公告)号：JPH04211545A
公开(公告)日：1992-08-03
申请号：JP3284991
申请日：1991-02-27
申请人： HITACHI LTD
发明人： NAKAYAMA HARUYUKI , SUKEGAWA FUMIO , TAKIYASU YOSHIHIRO
IPC分类号： H04J3/08 , H04L12/43 , H04L12/437 , H04Q11/04
摘要： PURPOSE:To fixedly provide a system control information transmission area in a transmission frame and to efficiently utilize the area. CONSTITUTION:A receiving control information processing part 17 transmits the information required to be transmitted to a downstream node out of system control information received from a receiving frame resolution part 41 to a transmission control information generation part 61. The transmission control information generation part 61 creates system control information to be stored in the system control information transmission area within the transmission frame and to be transmitted to downstream by utilizing the received information and system control information generated by its node. Thus, the system control information transmission area can be efficiently shared among each node.

5. 发明专利

JPH0865718A CROSSBAR PARTS FOR CROSSBAR NETWORK DEVICE 失效
公开(公告)号：JPH0865718A
公开(公告)日：1996-03-08
申请号：JP19660594
申请日：1994-08-22
申请人： HITACHI LTD
发明人： MURASE SHOICHI , AIMOTO TAKESHI , NAKAYAMA HARUYUKI
IPC分类号： H04Q3/02
摘要： PURPOSE: To facilitate assembling of a assembling of a crossbar network device even at a change of the connecting device number by providing a means which serves as a selector control means and sets the number of information processors, i.e., the data switching objects to be connected and also providing a means which changes the transfer data width. CONSTITUTION: When a selector setting signal 210 is sent to a register control part 300 of a selector control part from an arbiter, the part 300 generates a set signal 312 that is decided by a connecting device number selection signal 110 and a reception device address signal 212. The part 300 sends the signal 312 to an enable register 301 and a selection register 302. At the same time, the part 300 generates a register set value signal 310 that is decided by the signal 110 and a transmission device address signal 213 and sends the signal 310 to the register 302. When the value of the signal 312 is equal to 1, the register 301 sets the value of an enable signal 214 of its output at 1 and keeps this value. Meanwhile the register 302 sets a selection signal of its output at the value of the signal 312 and keeps this value when the value of the signal 312 is equal to 1.

6. 发明专利

JP2001357090A METHOD AND DEVICE FOR SYNTHESIZING LOGIC 失效
公开(公告)号：JP2001357090A
公开(公告)日：2001-12-26
申请号：JP2000177327
申请日：2000-06-13
申请人： HITACHI LTD
发明人： HIROTSU TEPPEI , FUJITA MAKOTO , SHIMAMURA KOTARO , YAMADA HIROMICHI , FUJII MASARU , NAKAYAMA HARUYUKI
IPC分类号： G06F17/50 , H01L21/82
摘要： PROBLEM TO BE SOLVED: To provide a method and a device for synthesizing logic, in which the delay of all the paths is brought close to a target value with one time of processing and the path between the sub-blocks can be easily optimized with a little labor in a short time. SOLUTION: The delay of the path inside the sub-block is brought close to the target value for every sub-block, and next, the delay of the path mutually between the plural sub-blocks is brought close to the target value. Concerning the regulation of the path delay between the sub-blocks, sub-block boundary parts corresponding to respective sub-blocks are exchanged. Thus, the optimization of a path between sub-blocks can be executed with one time of processing while sufficiently extracting the ability of a logic synthesizing tool as a result by eliminating necessity to put an input/output delay limit into the synthesis of the path between the sub-blocks by handling the path between the sub-blocks as a path inside the sub-block.

7. 发明专利

JPH08147250A MUTUAL COUPLE NETWORK AND COMMUNICATING METHOD FOR THE SAME 失效
公开(公告)号：JPH08147250A
公开(公告)日：1996-06-07
申请号：JP24130295
申请日：1995-09-20
申请人： HITACHI LTD
发明人： AIMOTO TAKESHI , INAI HIDENORI , MURASE SHOICHI , TANABE SHINICHI , HASHIMOTO KAZUHIRO , IWAMOTO HIROSHI , OGURO HIROSHI , HAYASHI TAKEHISA , NAKAYAMA HARUYUKI
IPC分类号： G06F15/173 , G06F15/16
摘要： PURPOSE: To utilize the network, which is applied to the mutual couple network for parallel processing, also as a network for decentralized processing by providing a block avoiding function. CONSTITUTION: A computer node is constituted by coupling a processor 130, memory 150, network adapter 110 and I/O device to a system bus 140. The network adapter 110 performs packet communication with the other computer node 100 through a packet communication network 190 equipped with a hardware flow control function and is composed of a DMA control part 120, buffer 121 for reception, buffer 122 for transmission and network transmission/reception part 118. When a packet is received while a receiving command inside the memory 150 is idle, the DMA control part 120 receives the packet by turning on a reception enable signal for the packet communication network 190 and aborts the received packet by using the network adapter 110.

8. 发明专利

JPH0895927A LARGE SCALE MUTUAL CONNECTION SWITCH 失效
公开(公告)号：JPH0895927A
公开(公告)日：1996-04-12
申请号：JP22758594
申请日：1994-09-22
申请人： HITACHI LTD
发明人： MURASE SHOICHI , NAKAYAMA HARUYUKI , AIMOTO TAKESHI , IWAMOTO HIROSHI
IPC分类号： G06F15/173 , G06F13/00 , G06F15/16 , H04L12/50 , H04Q3/545
摘要： PURPOSE: To provide a high-speed and large-scale mutual connection switch with a small amount by reducing the number of signal lines to be connected to respective parts consisting of the switch. CONSTITUTION: A large scale mutual connection switch 101 is provided with a signal line for connecting a communication control part 102 and a switch arbiter 103 while dividing all the communication control parts into groups with in multiple-to-one correspondence with wide bit width for every group and a signal line for connecting the communication control part and a bit slice switch 104 while dividing the input/output of the communication control parts into bits to connect them to respective bit slice switches in one-to-one correspondence. Thus, when these signal lines are provided, the communication and high- speed communication between the communication control part 102 which can not be bit-divided but comparatively only intermittently performs communication, and the switch arbiter 103 and between the communication control part 102, which continuously performs communication but can be bit-divided, and the bit slice switch 104 can be performed and the number of all the signal lines connected to the respective parts can be reduced.

9. 发明专利

JPH07152697A ROUGHLY COUPLED COMPUTER SYSTEM 失效
公开(公告)号：JPH07152697A
公开(公告)日：1995-06-16
申请号：JP29938293
申请日：1993-11-30
申请人： HITACHI LTD
发明人： MURAYAMA HIDEKI , YOSHIZAWA SATOSHI , NAKAYAMA HARUYUKI , MURASE SHOICHI , AIMOTO TAKESHI , INAI HIDENORI , HAYASHI TAKEHISA , IWAMOTO HIROSHI , HORIMOTO TORU
IPC分类号： G06F15/177 , G06F11/20 , G06F15/16
摘要： PURPOSE:To constitute the roughly coupled computer system which prevents an abnormal packet, etc., from being outputted to a computer coupling network and is improved in trouble resistance not only by starting substitute operation, but also by disconnecting an in-use system which is brought into trouble from the computer coupling network. CONSTITUTION:The computer coupling network 110 of the roughly coupled computer system is equipped with a means 111 which previously stores information showing the correspondence between a logical node number as an identifier specifying a reception-destination computer and the physical node number of a computer determined on the basis of actual connection relation and determines a corresponding physical node number on the basis of the logical node number specified from a transmission-source computer by using the stored information and a means 113 which performs a transfer process to the reception-destination computer having the determined physical node number.

10. 发明专利

JPH0689196A COMPUTER SYSTEM AND MAIN MEMORY CONTROLLER 失效
公开(公告)号：JPH0689196A
公开(公告)日：1994-03-29
申请号：JP23846492
申请日：1992-09-07
申请人： HITACHI LTD
发明人： KUROSAWA KENICHI , MORIOKA MICHIO , ISHIKAWA SUKETAKA , FUKUNAKA HIDETADA , NAKAYAMA HARUYUKI , IWAMOTO HIROSHI
IPC分类号： G06F9/46 , G06F11/00 , G06F11/10 , G06F11/14
摘要： PURPOSE:To avoid the system down regardless of the occurrence of a memory system fault with respect to the memory of a computer to which an error correction code is added. CONSTITUTION:If an error is detected by an error report signal C40 (C70), an error charging circuit D10 selects data A150 and A170 with a specific error correction code by selectors A140 and A160 instead of write data C100 (C110) to the memory transferred from a processor and sends these selected data to a memory bus B110 to write them in the memory. When data read from the memory is inputted from the memory bus B110, a charged error detecting circuit 020 detects whether this data is data A150 and A170 with the specific error correction code or not. When data with the specific error correction code is read out, the charged error detecting circuit D20 stops execution of only software which performed this read.

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