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31. 发明专利

JP2000322239A MULTIPLIER, MULTIPLIER/ACCUMULATOR, AND DATA PROCESSOR 失效
公开(公告)号：JP2000322239A
公开(公告)日：2000-11-24
申请号：JP13002999
申请日：1999-05-11
申请人： HITACHI LTD
发明人： YAMADA TETSUYA , TONOMURA MOTONOBU , ARAKAWA FUMIO , HAYASHI TOMOICHI
IPC分类号： G06F7/533 , G06F7/508 , G06F7/52 , G06F7/527 , G06F7/552 , G06F17/10
摘要： PROBLEM TO BE SOLVED: To obtain a multiplier which has a complete tree structure of 4-2 compressors. SOLUTION: A partial product generation circuit 103 which generates the partial product of a multiplicand X and a multiplier Y, a partial product inversion circuit (111-1 to 111-8) which partially inverts the output logic of the partial product generation circuit, 4-2 compressors 104, 112, and 113 which add the output of the partial product inversion circuit by a binary tree of a carry holding form, and a carry propagation means 105 which propagates carry of the output of 4-2 compressors are provided, and a correction bit '1' is set at the n-th bit position, and a correction bit of '-1' is set at the (2n-1)th bit position. Since 4-2 compressors are used, the complete tree of 4-2 compressors is constituted to achieve a regular layout structure.

32. 发明专利

JP2000235489A PROCESSOR 失效
公开(公告)号：JP2000235489A
公开(公告)日：2000-08-29
申请号：JP3549999
申请日：1999-02-15
申请人： HITACHI LTD
发明人： HAYASHI TOMOICHI , YAMADA TETSUYA , TSUNODA MASANOBU , NISHII OSAMU , ARAKAWA FUMIO
IPC分类号： G06F9/38 , G06F9/30
摘要： PROBLEM TO BE SOLVED: To provide a processor generating different exceptions at the time of executing an instruction for a sub-arithmetic unit when the sub-arithmetic unit is not added to a CPU, and at the time of designating the non-use of the sub-arithmetic unit by software. SOLUTION: When a mode bit C settable by a program supplied from a mode register 40 does not instruct the inhibition of the use of a sub-arithmetic unit, and an additional state identification signal B supplied from a signal generating circuit (not shown in a figure) indicates that a sub-arithmetic unit 20A is not added to a CPU 10, a first exception is generated by a judging circuit 30 and an exception generating circuit in response to an instruction to use the sub-arithmetic unit. When the mode bit C instructs the inhibition of the use of the sub-arithmetic unit, a second exception is generated by the judging circuit 30 and the exception generating circuit in response to the instruction to use the sub-arithmetic unit regardless of whether or not the additional state identification signal B indicates that the sub-arithmetic unit is added to the CPU.

33. 发明专利

JPH10187420A DIVISION AND SQUARE ROOT EXTRACTION ARITHMETIC UNIT 失效
公开(公告)号：JPH10187420A
公开(公告)日：1998-07-21
申请号：JP35733196
申请日：1996-12-26
申请人： HITACHI LTD
发明人： YAMADA TETSUYA , TONOMURA MOTONOBU , ARAKAWA FUMIO , TOTSUKA YONETARO
IPC分类号： G06F7/552
摘要： PROBLEM TO BE SOLVED: To achieve the acceleration of arithmetic in SRT division/square root extraction arithmetic and to reduce circuit scale. SOLUTION: A quotient digit selector circuit (QSL) 1009 and a partial remainder high-order digit prediction circuit (REL) 1010 are provided by synthesizing logics based on a quotient selection/partial remainder high-order digit prediction table. A partial remainder high-order digit determination circuit (REM) 1011 generates the high-order three digits of partial remainder based on the high-order two digits of partial remainder from the REL 1010, one bit of sum and one bit of carry from a conservative adder (CSA) 1008. The QSL 1009 generates high-order four digits of partial remainder based on high-order three digits of partial remainder from the REM 1011, one bit of sum and one bit of carry from the CSA 1008 so that a quotient digit can be found. The REL 1010 generates high-order four digits of partial remainder from the REM 1011, one bit of sum and one bit of carry from the CSA 1008 and finds the predictive value of high-order two digits of partial remainder based on these generated four digits, one digit of divided/partial root extracted value and the quotient digit from the QSL 1009.

34. 发明专利

JPH0695967A DATA PROCESSOR 失效
公开(公告)号：JPH0695967A
公开(公告)日：1994-04-08
申请号：JP24295892
申请日：1992-09-11
申请人： HITACHI LTD
发明人： ARAKAWA FUMIO , UCHIYAMA KUNIO
IPC分类号： G06F12/08 , G06F12/10
摘要： PURPOSE:To quickly execute the partial clear of a direct map type or set associative type buffer memory. CONSTITUTION:This data processor is provided with a latch 6 for storing a comparing value for the partial clear of the buffer memory and control logic 8 for asserting a clear signal when a tag read out from a tag array 2 is compared with the comparing value of the latch 6 by a comparator 7 and both the values coincide with each other, and generating a hit signal and a new V flag based upon a V flag and coincident, clear and type signals. When coincidence is detected by the comparator 7, the V flag of an entry is turned from a clear queuing state to an invalid state. Consequently, the partial clear of the buffer memory can quickly be executed independently of capacity.

35. 发明专利

JPH05120013A DATA PROCESSOR HAVING BRANCH INSTRUCTION BUFFER 失效
公开(公告)号：JPH05120013A
公开(公告)日：1993-05-18
申请号：JP28103091
申请日：1991-10-28
申请人： HITACHI LTD
发明人： NARITA SUSUMU , ARAKAWA FUMIO , UCHIYAMA KUNIO , AOKI HIROKAZU
IPC分类号： G06F9/38 , G06F9/42
摘要： PURPOSE:To speed up the branch processing of a microprocessor and to especially speed up a non-conditional branch instruction including a return instruction. CONSTITUTION:A branch instruction address, a branch destination address, and a branch instruction type are made into a group and they are held in a branch instruction buffer BW102 as branch history information. A return buffer RB103 holding a return address is provided. Retrieval is executed by using a prefetch address. At the time of hit, the branch destination address of either BW102 or RB103 is selected by using the branch instruction type, and the prefetch address is switched so as to execute prebranching. An overhead at the time of branching can be made zero. A data processor can be applied to all the branch instructions including the return instruction.

36. 发明专利

JPH04186594A MULTI-PORT MEMORY 失效
公开(公告)号：JPH04186594A
公开(公告)日：1992-07-03
申请号：JP31399990
申请日：1990-11-21
申请人： HITACHI LTD
发明人： OKADA TETSUHIKO , SUZUKI MAKOTO , NARITA SUSUMU , ARAKAWA FUMIO , UCHIYAMA KUNIO
IPC分类号： G11C11/41
摘要： PURPOSE:To access to a most priority address line when the same address is input to different address lines, and to simultaneously write a plurality of data by adding a simple logic by providing a priority order at input address lines. CONSTITUTION:A priority processor 600 inputs word selection lines WS10 - WS1n, WS20 - WS2n from address decoders 110, 120, preferentially processes the address of an address bus 101, and sends word lines W10 - W1n, W20 - 2n to a memory cell array 300. When a word selection line WS1i is selected, the SW2i is invalidated, and when the same address is input, only a word line W1i to the bus 101 is validated. A coincidence detector 700 generates a positive polarity coincidence signal 701 when the addresses of the buses 101, 102 are equal, generates a negative polarity coincidence signal when both the addresses are difference, and transfers an access or not the same address to a data output unit 500. When the configuration is provided in a multi-port memory, a plurality can be simultaneously written without overhead.

37. 发明专利

JPH04175959A MICROPROCESSOR 失效
公开(公告)号：JPH04175959A
公开(公告)日：1992-06-23
申请号：JP30239990
申请日：1990-11-09
申请人： HITACHI LTD
发明人： NARITA SUSUMU , ARAKAWA FUMIO , OKADA TETSUHIKO , UCHIYAMA KUNIO , MATSUMOTO YOSHIHIRO
IPC分类号： G06F13/40 , H03K19/0175
摘要： PURPOSE:To obtain large tolerance to a noise, to suppress the generation of a through current on a data bus, and to suppress the power consumption and calorific value by setting a period wherein the bus is driven shorter than one cycle. CONSTITUTION:A clock signal phi1 is added to the control signals 102 and 105 of ternary inverters 103 and 106 to set the driving period of the ternary inverters 103 and 106 shorter than one cycle, and feedback circuits 107 - 110 for fixing the value on the bus 100 in a period wherein neither of the ternary inverters 103 and 106 drives the bus are added. Consequently, circuit constitution which is tolerant to a noise is obtained, the through current which is generated owing to skew is suppressed, and the power consumption and calorific value of the whole VLSI chip are reduced.

38. 发明专利

JPH04175929A MICROPROCESSOR 失效
公开(公告)号：JPH04175929A
公开(公告)日：1992-06-23
申请号：JP30241590
申请日：1990-11-09
申请人： HITACHI LTD
发明人： ARAKAWA FUMIO , OKADA TETSUHIKO , NARITA SUSUMU
IPC分类号： G06F9/38
摘要： PURPOSE:To expedite register update by performing the register update by the addition of the latest value without waiting the end of register reference. CONSTITUTION:For register update halfway in a pipeline, a register update control mechanism 16 latches the value of a bus C5 in a latch A, inhibits the same register from being updated halfway in the pipeline until the final stage of the pipeline is started, and transfers the value of the latch A in the final stage of the pipeline to a latch B. For register update at the end of the pipeline, the value of a bus C'10 is latched in the latch B. A register reference control mechanism 17 selects the latch A for register reference of next and succeeding instructions from the register update halfway in the pipeline to the end of the final stage of the pipeline or the latch B for other cases, and outputs the value to a bus A2, a bus B3, a bus A'8, or bus B'9. Consequently, the register update can be expedited.

39. 发明专利

JPH04175928A MICROPROCESSOR 失效
公开(公告)号：JPH04175928A
公开(公告)日：1992-06-23
申请号：JP30241690
申请日：1990-11-09
申请人： HITACHI LTD
发明人： NARITA SUSUMU , OKADA TETSUHIKO , ARAKAWA FUMIO
IPC分类号： G06F9/38
摘要： PURPOSE:To speed up processing by buffering information, indicating whether or not respective process stages are used, as to plural instructions from an instruction coding or decoding result and transferring data not through the respective process stages by using the information. CONSTITUTION:An instruction deciding part 3 decodes instructions 10 which are inputted one after another by an instruction decoder 20 and generates their instruction addresses by an instruction address generator 22 at the same time. Decoding information 31 of the obtained instructions and the instruction addresses 32 are stored in a decoding information buffer(DIB) 23. Plural pieces of instruction decoding information and instruction addresses can be held in the DIB 23, and processes which can be executed in parallel are found in the DIB among them and outputted as stage-classified control information 11-1. A stage-classified answer signal 11-3 is an answer signal corresponding to an execution request which is made by using the signal 11-1 and an instruction address 11-2 is used by an address calculation part 4 for address calculation. Consequently, the instruction execution can be speeded up.

40. 发明专利

JPH0477925A MICROPROCESSOR 失效
公开(公告)号：JPH0477925A
公开(公告)日：1992-03-12
申请号：JP19066190
申请日：1990-07-20
申请人： HITACHI LTD
发明人： NARITA SUSUMU , ARAKAWA FUMIO , OKADA TETSUHIKO , UCHIYAMA KUNIO
IPC分类号： G06F9/30 , G06F9/32 , G06F9/38 , G06F12/04
摘要： PURPOSE:To improve the maximum throughput of instruction decoding performance by assuming the instruction length of a preceding instruction so as to decode a succeeding instruction among the instructions which are simultaneously decoded. CONSTITUTION:A control part PCNT judges whether instruction codes which respective instruction decoders ID0 and ID1 process are the instructions which can be decoded in respective instruction decoders or not. When they are the instruction decoders decoding the instructions having form which cannot be decoded, the decoding result of the instruction code succeeding the instruction is entirely ignored. When all the instruction decoders decode the instruction having the shortest instruction form as the result of judgement, all decoding results are set to be effective. At that time, the throughput of the instruction decoding is maximum and the instructions whose number is equal to that of the instruction decoders are processed in one cycle. Thus, the maximum throughput of instruction decoding performance can be improved.

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