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1. 发明专利

JP2009110353A Microcontroller and control system 审中-公开
标题翻译：微控制器和控制系统
公开(公告)号：JP2009110353A
公开(公告)日：2009-05-21
申请号：JP2007282959
申请日：2007-10-31
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： KATO NAOKI , YAMADA TETSUYA , ARAKAWA FUMIO , YAMADA HIROMICHI , OBO SHIGERU , ISHIKAWA MAKOTO
IPC分类号： G06F7/76
CPC分类号： G06F9/30025 , G06F7/483 , G06F9/3001 , H03M7/24
摘要： PROBLEM TO BE SOLVED: To suppress an increase in code amount by a program code for performing floating-point arithmetic, especially by its variable, and to reduce a processing overhead for converting fixed-point data into floating-point data. SOLUTION: The microcontroller (1) has: a floating-point converter (32) for inputting integer data and corresponding decimal point position data as fixed-point data to a control system and converting the input data into floating-point data by obtaining a fraction part, an exponent part, and a sign of a floating type from the input data; and a floating-point arithmetic logic unit (38) for receiving the output of the floating-point converter and calculating the floating-point data. The floating-point converter acquires the exponent part by performing addition and subtraction of the decimal point position data (ESP2) and the shift amount of the fraction part to the integer data. COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：通过用于执行浮点运算的程序代码，特别是通过其变量来抑制代码量的增加，并且减少用于将定点数据转换为浮点数据的处理开销。微控制器（1）具有：浮点转换器（32），用于将整数数据和对应的小数点位置数据作为定点数据输入到控制系统，并将输入数据转换为浮点数据从输入数据中获取浮动类型的分数部分，指数部分和符号; 以及用于接收浮点转换器的输出并计算浮点数据的浮点算术逻辑单元（38）。浮点转换器通过对小数点位置数据（ESP2）的加减运算和分数部分的移位量进行整数取得指数部分。版权所有（C）2009，JPO＆INPIT

2. 发明专利

JP2008139964A Data processor 有权
标题翻译：数据处理器
公开(公告)号：JP2008139964A
公开(公告)日：2008-06-19
申请号：JP2006323537
申请日：2006-11-30
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： ARAKAWA FUMIO
IPC分类号： G06F9/38
CPC分类号： G06F9/3867 , G06F9/30105 , G06F9/30181 , G06F9/325 , G06F9/381 , G06F9/3828 , G06F9/3885 , G06F9/3891
摘要： PROBLEM TO BE SOLVED: To provide a highly efficient and high performance processor for achieving efficient data transfer between a plurality of instruction flows, and for dividing a program into a plurality of instruction flows for execution. SOLUTION: A data processor having normal functions is configured as the integrated body of processors (CPU1 and CPU2) which define an instruction having the write instruction of another instruction flow into a reference register and an instruction having a reference register invalidation instruction, and execute a plurality of simple instruction flows. In executing the instruction having the write instruction of the other instruction flow into the reference register, whether or not a write register is invalid is confirmed, and when the write register is not invalid, writing is not executed until it becomes invalid, and when the write register is invalid, writing is executed. The instruction having the reference register invalidation instruction is executed, the register which has finished reference is invalidated. Furthermore, when the reference register is invalid, the execution of the reference instruction is suppressed until it becomes valid. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供一种高效率和高性能的处理器，用于实现多个指令流之间的有效数据传输，并且用于将程序划分为多个指令流以供执行。解决方案：具有正常功能的数据处理器被配置为处理器（CPU1和CPU2）的集成体，其将具有另一指令流的写指令的指令定义到参考寄存器中，以及具有参考寄存器无效指令的指令，并执行多个简单的指令流。在将具有其他指令流的写入指令执行到参考寄存器中的指令中，确认写入寄存器是否无效，并且当写入寄存器不为无效时，直到无效之后才执行写入，并且当写入寄存器无效，写入被执行。执行具有参考寄存器无效指令的指令，已完成引用的寄存器无效。此外，当参考寄存器无效时，参考指令的执行被抑制直到其变为有效。版权所有（C）2008，JPO＆INPIT

3. 发明专利

JP2006352706A MICROPROCESSOR, NETWORK SYSTEM AND COMMUNICATION METHOD 审中-公开
公开(公告)号：JP2006352706A
公开(公告)日：2006-12-28
申请号：JP2005178538
申请日：2005-06-17
申请人： HITACHI LTD
发明人： KATO NAOKI , ARAKAWA FUMIO
IPC分类号： H04L29/10 , B60R16/023 , G06F13/00 , G06F13/24
摘要： PROBLEM TO BE SOLVED: To provide a microprocessor and communication method with which a processor is efficiently operated and a reply of good response can be returned to a transmitting side microprocessor by reducing, as little as possible, interruption to a CPU that occurs when a microprocessor connected by a network receives a packet from the network. SOLUTION: A microprocessor 3 comprises a CPU and a communication module. The communication module includes a register 22 for storing information managed by the microprocessor 3. The communication module compares information on a prescribed bit position within a packet input via a network with information held in the register and judges whether the CPU is to perform processing corresponding to packet reception in accordance with a comparison result. COPYRIGHT: (C)2007,JPO&INPIT

4. 发明专利

JP2006134203A Distributed control system 有权
标题翻译：分布式控制系统
公开(公告)号：JP2006134203A
公开(公告)日：2006-05-25
申请号：JP2004324679
申请日：2004-11-09
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： KATO NAOKI , ARAKAWA FUMIO
IPC分类号： G06F9/48 , G06F9/50 , G06F11/20 , G06F11/34
CPC分类号： G05B19/0421 , G05B2219/25229 , G05B2219/25231
摘要： PROBLEM TO BE SOLVED: To provide a load distributed system for efficiently driving each control unit in addition to ensuring real time and improving failure proof in addition to ensuring the real time, as a distributed control system in which a plurality of control units are connected. SOLUTION: Each task is given a deadline to be a request time until task completion or information on cycle at which the task is activated and, in accordance with the deadline or task cycle, a control unit for executing the task is selected. A first control circuit is connected to a sensor and actuator with a dedicated path in which a high-speed response time is easily ensured and another control circuit is connected to the sensor and actuator with a network. When the first control circuit is normally operated and has sufficient processing capability, the first control circuit is used for control, whereas it has a failure or insufficient processing capability, other control circuits are used. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：除了确保实时以外，除了确保实时以外，还提供一种用于有效地驱动每个控制单元的负载分布式系统，作为其中多个控制单元被连接。解决方案：每个任务都有一个截止期限，作为完成任务之前的请求时间或任务被激活的周期信息，并根据最后期限或任务周期选择用于执行任务的控制单元。第一控制电路连接到传感器和致动器，其具有容易确保高速响应时间的专用路径，并且另一控制电路通过网络连接到传感器和致动器。当第一控制电路正常工作并且具有足够的处理能力时，第一控制电路用于控制，而其具有故障或处理能力不足，则使用其它控制电路。版权所有（C）2006，JPO＆NCIPI

5. 发明专利

JP2005338986A Data processing unit and semiconductor device 有权
标题翻译：数据处理单元和半导体器件
公开(公告)号：JP2005338986A
公开(公告)日：2005-12-08
申请号：JP2004154232
申请日：2004-05-25
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： ARAKAWA FUMIO
IPC分类号： G06F1/28 , G06F1/30 , G06F1/32 , G06F15/78 , H01L21/822 , H01L27/04
CPC分类号： G06F1/3203 , G06F1/3287 , G06F9/3836 , G06F9/3869 , Y02D10/171
摘要： PROBLEM TO BE SOLVED: To allow a semiconductor device having a plurality of modules to exhibit the appropriate performance of each module, while managing power on the basis of distributed management, and managing the power permitted for a chip as a whole. SOLUTION: A predetermined power consumption value is defined for each module. The predetermined power consumption value is an amount defined, while the permissible power values of the plurality of modules are taken into consideration. Each of the modules reports the difference between the predetermined power consumption value and the value of actually consumed power to other modules as the amount of extra power. Each of the modules can process data for an amount below the predetermined power consumption value, even without using the extra power coming from the other modules, so as to avoid deadlock. When the amount of extra power is reported from the other modules, the amount of power equal to the predetermined power consumption value and the amount of extra power are set as the amount of power consumable for data processing. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：为了允许具有多个模块的半导体器件在分散管理的基础上管理电力，并且管理整体上的芯片所允许的功率，表现出每个模块的适当性能。
解决方案：为每个模块定义预定的功耗值。预定功耗值是限定的量，同时考虑多个模块的容许功率值。每个模块报告预定功耗值与其他模块的实际消耗功率的值之间的差异作为额外功率的量。即使没有使用来自其他模块的额外功率，每个模块也可以处理低于预定功耗值的数据，以避免死锁。当从其他模块报告额外功率的量时，将等于预定功耗值的功率量和额外功率量设置为用于数据处理的功耗量。版权所有（C）2006，JPO＆NCIPI

6. 发明专利

JP2005335548A Vehicular control system, control system and control method 有权
标题翻译：车辆控制系统，控制系统和控制方法
公开(公告)号：JP2005335548A
公开(公告)日：2005-12-08
申请号：JP2004157295
申请日：2004-05-27
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： NAONO TAKESHI , SHIMIZU MASAAKI , ARAKAWA FUMIO , KANEKAWA NOBUYASU , SAKURAI KOHEI , HOSHINO MASATOSHI , YOSHIMURA KENTARO
IPC分类号： B60R16/02 , B60W10/00 , B60W10/02 , B60W10/04 , B60W10/06 , B60W10/10 , B60W10/12 , B60W10/18 , B60W10/184 , B60W10/20 , B60W10/22 , F02D45/00 , G05B13/02 , B60K41/00 , B60K41/28
CPC分类号： G05B13/024
摘要： PROBLEM TO BE SOLVED: To reduce the man hour required for tuning of control parameters. SOLUTION: The vehicular control system comprises a user parameter input unit Sa to input user parameters according to the operation of a user, an external parameter input unit Sb to input external parameters attributable to the external environment, a plurality of objective functions which are set for each control characteristic to obtain internal parameters for each control object from the user parameters and the external parameters, a policy setting unit to set the policy to indicate the control index of the user to the plurality of objective functions, and a policy node 1 which weighs the plurality of objective functions based on the policy, adjusts the internal parameters so as to be optimum (minimum or maximum) between the plurality of objective functions to agree with the policy, and gives a command to the control node corresponding to the internal parameters. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：减少调节控制参数所需的人工时间。解决方案：车辆控制系统包括用户参数输入单元Sa，以根据用户的操作输入用户参数;外部参数输入单元Sb，用于输入归因于外部环境的外部参数，多个目标函数，根据用户参数和外部参数为每个控制对象设定内部参数，策略设置单元设置策略以指示用户对多个目标函数的控制索引，以及策略节点 1，其基于策略来对多个目标函数进行权重，调整内部参数以便在多个目标函数之间是最优（最小或最大）以符合策略，并且向对应于该策略的控制节点发出命令内部参数。版权所有（C）2006，JPO＆NCIPI

7. 发明专利

JPH10124484A DATA PROCESSOR AND DATA PROCESSING SYSTEM 失效
公开(公告)号：JPH10124484A
公开(公告)日：1998-05-15
申请号：JP27343296
申请日：1996-10-16
申请人： HITACHI LTD
发明人： ARAKAWA FUMIO , NAKAGAWA NORIO , YAMADA TETSUYA , TOTSUKA YONETARO
IPC分类号： G06F7/38 , G06F7/487 , G06F7/50 , G06F7/509 , G06F7/53 , G06F7/544 , G06F7/548 , G06F9/30 , G06F9/302 , G06F9/38 , G06F17/10 , G06T1/20 , G06F7/52
摘要： PROBLEM TO BE SOLVED: To perform a vector conversion operation or an inner product operation using the floating points at a high speed and with high accuracy. SOLUTION: The result of an inner product operation or a vector conversion operation is obtained by giving eight floating points to four multipliers 220a to 220d for their parallel operations and adding together these multiplication results in parallel to each other via a single 4-input adder 226. A circuit 227 normalizes and rounds the output of the adder 226. Thus, an inner product can be calculated via the multiplication and the addition which are carried out once in parallel to each other. Then no rounding process is required for the double input in every product sum operation to shorten the latency of the inner product operation and to improve the arithmetic accuracy. Furthermore, just a single circuit suffices for normalization, etc., and accordingly the increase of the circuit scale is minimized. As a result, an inner product operation, etc., using the floating points can be performed at a high speed and with high accuracy.

8. 发明专利

JPH05233271A 失效
公开(公告)号：JPH05233271A
公开(公告)日：1993-09-10
申请号：JP3315692
申请日：1992-02-20
申请人： HITACHI LTD
发明人： ARAKAWA FUMIO , NARITA SUSUMU , UCHIYAMA KUNIO
IPC分类号： G06F9/38 , G06F9/22 , G06F9/28 , G06F9/30 , G06F9/318
摘要： PURPOSE:To provide a data processor capable of efficiently processing both of a reference instruction and a high function instruction. CONSTITUTION:When two reference instructions are supplied to instruction decoders 21, 22, instruction execution parts 51, 52 simultaneously execute the two reference instructions based upon decoded outputs from the decoders 21, 22 without using a microprgram ROM 30. When a high function instruction is supplied to one decoder 21, one execution part 51 selects the output of one decoder 21 and executes processing without using a microinstruction outputted from the ROM 30 in the 1st processing, and in the 2nd processing, the execution part 51 executes processing by selecting the microinstruction from the ROM 30. Since necessity of using the ROM 30 is eliminated at the time of executing the reference instruction, the capacity and the area of the ROM and power consumption corresponding to the reference instruction can be reduced.

9. 发明专利

JP2007034359A Distributed control system 审中-公开
标题翻译：分布式控制系统
公开(公告)号：JP2007034359A
公开(公告)日：2007-02-08
申请号：JP2005212238
申请日：2005-07-22
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： HYODO AKIHIKO , KATO NAOKI , ARAKAWA FUMIO
IPC分类号： G06F9/50 , G06F9/48
CPC分类号： G05B19/042 , B60W2050/0297 , G05B2219/25229 , G05B2219/2637 , G06F9/4856 , G06F9/5033 , G06F9/5044
摘要： PROBLEM TO BE SOLVED: To provide a distributed control system in which a plurality of controllers are connected to one another by a network and which is capable of transferring tasks, for execution on other controllers, with properties specific for the controllers, where input and output processes are required or data stored in specific controllers are used.
SOLUTION: To execute the transfer tasks specific for the controllers for execution on the other controllers, the transferring controller is provided with functions of collecting input data and context information in a storage area and transferring them to a destination controller, in addition to its original functions. The destination controller is provided with, functions of storing the data sent from the transferring controller in the storage area, performing computations, and returns the results to the transferring controller. The program of the task performing computation processes is included in both the destination controller and the transferring controller, and the destination controller determines a reference address using an appropriate method for processing the task.
COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供一种分布式控制系统，其中多个控制器通过网络彼此连接，并且能够以特定于控制器的特性在其他控制器上传送任务以执行任务，其中需要输入和输出过程或使用存储在特定控制器中的数据。
解决方案：为了执行特定于控制器在其他控制器上执行的传输任务，转移控制器具有在存储区域中收集输入数据和上下文信息并将其传送到目的地控制器的功能，其原有功能。目的地控制器设置有将从传送控制器发送的数据存储在存储区域中的功能，执行计算，并将结果返回给传送控制器。执行计算处理的任务的程序包括在目的地控制器和传送控制器中，并且目的地控制器使用用于处理该任务的适当方法来确定参考地址。版权所有（C）2007，JPO＆INPIT

10. 发明专利

JP2003177911A ARITHMETIC UNIT AND INFORMATION PROCESSOR USING THE ARITHMETIC UNIT 审中-公开
公开(公告)号：JP2003177911A
公开(公告)日：2003-06-27
申请号：JP2001379549
申请日：2001-12-13
申请人： HITACHI LTD
发明人： YAMADA TETSUYA , ARAKAWA FUMIO
IPC分类号： G06F7/00 , G06F9/30
摘要： PROBLEM TO BE SOLVED: To provide a computing unit which can decrease the number of bits used for operation. SOLUTION: Operation data are provided with an additional bit representing size information and according to the size information, operation is carried out with minimum data width. Two input data are divided into high-order and low-order parts and size bits S1 and S2 are provided by the data units. When only low-order sides of both the two input data are effective, input data and carry-in CIU of a high-order side adder 107 are fixed to stop the high-order side adder from consuming electric power. Only the low-order side of one input data is effective and the high-order and low-order sides of the other input data are effective, the code of the effective data of the lower-order side are expanded to equalize the data widths of the two inputs to each other and the operation is carried out. When the high-order and low-order sides of the two input data are both effective, the operation is performed by using high-order and low-order computing units 107 and 108. Consequently, it is decided whether high-order and low-order sides are effective or ineffective by the data units to perform operations always with the minimum effective data width and the power consumption is made less than that of conventional computing units which always use the maximum width. COPYRIGHT: (C)2003,JPO

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