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1. 发明专利

JP2012013018A Steam turbine rotor 审中-公开
标题翻译：蒸汽轮机转子
公开(公告)号：JP2012013018A
公开(公告)日：2012-01-19
申请号：JP2010151088
申请日：2010-07-01
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： SUZUKI MAKOTO , YODA HIDEO
IPC分类号： F01D5/06 , F01D5/30 , F01D25/00
摘要： PROBLEM TO BE SOLVED: To provide a steam turbine rotor capable of, even when highly moist steam and impurities enter the clearance between a moving blade and a wheel, easily discharging the steam and impurities during the operation of a steam turbine.SOLUTION: The steam turbine rotor includes: a shaft 1; the wheel 2 that is installed on a circumference of the shaft 1, has a wheel groove 22, and has two or more recessed parts 23 disposed in the wheel groove 22 in the radial direction of rotor; a moving blade 3 that is provided with an implant part 32 having two or more projections 33 to be fitted to two or more recessed parts 23 and is combined with the wheel 2 via the implant part 32; and discharge holes 41 that communicates at least one of the two or more recessed parts 23 and an outer peripheral surface 25 of the wheel 2.
摘要翻译：要解决的问题：为了提供一种蒸汽轮机转子，即使当高湿度蒸汽和杂质进入活动叶片和轮子之间的间隙时，也能够在蒸汽轮机的操作期间容易地排出蒸汽和杂质。蒸汽轮机转子包括：轴1; 安装在轴1的圆周上的车轮2具有车轮槽22，并且在转子的径向具有设置在车轮槽22中的两个以上的凹部23，具有植入部32的移动叶片3，该植入部32具有两个以上的突起33，以配合到两个以上的凹部23，并通过植入部32与轮2组合; 以及与两个以上的凹部23和轮2的外周面25中的至少一个连通的排出孔41.版权所有（C）2012，JPO＆INPIT

2. 发明专利

JP2008171218A Personal identification method and personal identification system 审中-公开
标题翻译：个人识别方法和个人识别系统
公开(公告)号：JP2008171218A
公开(公告)日：2008-07-24
申请号：JP2007003987
申请日：2007-01-12
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： SUZUKI MAKOTO , MATSUMOTO SHINGO
IPC分类号： G07F7/12 , G06Q10/00 , G06Q20/18 , G06Q20/32 , G06Q20/40 , G06Q40/00 , G06Q40/02 , G06Q50/00 , G07D9/00 , H04L9/32
摘要： PROBLEM TO BE SOLVED: To provide a method for preventing the illegal use of an automatic transaction device due to the impersonation of a third person, and for preventing personal identification from failing without deteriorating security.
SOLUTION: In this personal identification device and method, a portable communication terminal and an automatic transaction device are respectively provided with: a storage function for storing at least one of a plurality of biological information of a user and information necessary for transaction; a biological information input function for inputting at least one of the plurality of biological information of the user; a communication means for transmitting and receiving the input biological information and the stored biological information and the information necessary for transaction between the portable communication terminal and the automatic transaction device; and a collation function for comparing and collating the biological information input for performing personal identification with the stored biological information, and the stored biological information with each other, and the mutual information necessary for transaction with each other concerning information matching or similarity, and only when the collation result is satisfactory as personal identification information, the transaction by the automatic transaction device is made possible.
COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供一种防止由于第三人造成的非法使用自动交易装置的方法，并且用于防止个人身份识别而不会恶化安全性。在该个人识别装置和方法中，便携式通信终端和自动交易装置分别具有：用于存储用户的多个生物信息和交易所需的信息中的至少一个的存储功能; 用于输入用户的多个生物信息中的至少一个的生物信息输入功能; 用于发送和接收所述输入生物信息和所存储的生物信息和所述便携式通信终端与所述自动交易装置之间交易所需的信息的通信装置; 以及用于将用于执行个人识别的生物信息输入与所存储的生物信息和存储的生物信息相互比较和对照的对照功能，以及关于信息匹配或相似性的彼此交易所需的互信息，并且仅当归类结果令人满意的是个人识别信息，自动交易装置的交易成为可能。版权所有（C）2008，JPO＆INPIT

3. 发明专利

JP2006120371A Personal digital assistant and self-diagnostic method of personal digital assistant 有权
标题翻译：个人数字助理和个人数字助理自诊断方法
公开(公告)号：JP2006120371A
公开(公告)日：2006-05-11
申请号：JP2004304977
申请日：2004-10-19
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： KANOUDA TAMAHIKO , KIKUCHI MUTSUMI , NORIMATSU YASUAKI , FUJITA EISAKU , SUZUKI MAKOTO , ISHII SATOSHI , MURAKAWA MANABU
IPC分类号： H01M8/04 , G06F1/26 , H01M8/00
CPC分类号： Y02E60/50
摘要： PROBLEM TO BE SOLVED: To provide a personal digital assistant capable of conducting self-diagnosis and power generation retrying in a state of no-recognition by a user in a case where a secondary battery and a fuel cell are mounted and charge and discharge are effectively conducted. SOLUTION: When the personal digital assistant is transited between an operation state and a standby state, self-diagnosis is conducted. The fuel cell charges the secondary battery at current of rated value I1 (S42), and when the output voltage of a booster DC/DC converter is dropped (when PG=L), charge current is decreased to a rated value 12 and aging is conducted (S44). After aging is conducted for 60 seconds, current is returned to the rated value I1 and charge is conducted (S42). These operations are repeated 30 times. In the aging (S44), when the output voltage of the booster DC/DC converter is dropped (when PG=L), the aging is stopped (S48), and after 20 seconds, aging is executed again (S44), and these operations are repeated 10 times. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供一种能够在安装二次电池和燃料电池的情况下以用户不识别的状态进行自诊断和发电重试的个人数字助理，有效地进行排放。
解决方案：当个人数字助理在操作状态和待机状态之间转换时，进行自我诊断。燃料电池在额定电流I1（S42）的电流下对二次电池充电，当升压型DC / DC转换器的输出电压下降（PG = L时），充电电流降至额定值12，老化进行（S44）。老化进行60秒后，电流返回到额定值I1，进行充电（S42）。这些操作重复30次。在老化（S44）中，当升压型DC / DC转换器的输出电压下降（PG = L）时，老化停止（S48），20秒后再次老化（S44），这些操作重复10次。版权所有（C）2006，JPO＆NCIPI

4. 发明专利

JP2003124432A SEMICONDUCTOR DEVICE AND ELECTRONIC DEVICE INTEGRATING THE SEMICONDUCTOR DEVICE 审中-公开
公开(公告)号：JP2003124432A
公开(公告)日：2003-04-25
申请号：JP2001320073
申请日：2001-10-18
申请人： HITACHI LTD
发明人： SUZUKI MAKOTO , KIKUCHI TAKAFUMI , SUGITA NORIHIKO , SHIRAKAWA SEIICHI
IPC分类号： H01L23/12 , G11C11/00 , H01L21/56 , H01L23/50 , H01L23/538 , H01L25/065 , H01L25/07 , H01L25/18
摘要： PROBLEM TO BE SOLVED: To provide a small-sized and low-cost semiconductor device formed that a synchronous dynamic memory and a flash memory are integrated into a single sealing body. SOLUTION: A flash memory chip and a synchronous dynamic memory chip (an SDRAM chip) are fixed in a parallel state on the main surface of a wiring substrate, and other SDRAM chip is fixed on the flash memory chip. The electrodes of each semiconductor chip are respectively exposed, and the electrode is connected to the electrode of the wiring substrate through a wire. On the main surface side of the wiring substrate, a sealing body formed of insulating resin is formed in a manner to cover the semiconductor chip and a wire. Since the sealing body is formed by cutting a batch sealing body, formed by batch sealing, through dicing, the side of the sealing body forms a cut surface. Bump electrodes are situated in an array-form state on the back of the wiring substrate.

5. 发明专利

JP2000181681A DATA PROCESSOR 失效
公开(公告)号：JP2000181681A
公开(公告)日：2000-06-30
申请号：JP35867598
申请日：1998-12-17
申请人： HITACHI LTD
发明人： OKUBO MICHIO , SUZUKI MAKOTO , SUZUKI YUJI
IPC分类号： G06F7/00 , G06F7/76
摘要： PROBLEM TO BE SOLVED: To provide a data processor which fast normalizes operation results to be capable of improving an operation frequency. SOLUTION: A logical circuit which contains a computing element 101, a preceding 0 predictor 102 and a preceding 1 predictor 103 and normalizes operation results is provided with a 1st barrel shifter 104 which shifts an output of the element 101 with an output 114 of the preceding 0 predictor 102 and a 2nd barrel shifter 105 which shifts the output of the element 101 with an output 115 of the preceding 1 predictor 105. According to this configuration, it is possible to fast normalize operation results.

6. 发明专利

JPH11122094A SEMICONDUCTOR INTEGRATED CIRCUIT 失效
公开(公告)号：JPH11122094A
公开(公告)日：1999-04-30
申请号：JP22400398
申请日：1998-08-07
申请人： HITACHI LTD
发明人： TACHIBANA MASARU , SUZUKI MAKOTO , HIGUCHI HISAYUKI
IPC分类号： H01L21/8249 , H01L27/06 , H03K17/04 , H03K17/567 , H03K19/017 , H03K19/08 , H03K19/0944
摘要： PROBLEM TO BE SOLVED: To provide high speed and to reduce leakage current in a semiconductor integrated circuit, composed of a MOSFET and a bipolar transistor for driving a load by the bipolar transistor. SOLUTION: In this semiconductor integrated circuit composed of a MOSFET 106 and a bipolar transistor 110 for driving the load by a bipolar transistor 110, CMOS circuits 112 and 113 supplied with a prescribed positive power supply voltage V2 are further provided on the same substrate and a positive operation voltage VCC, which is higher than the positive power supply voltage V2 supplied to the CMOS circuits 112 and 113 is supplied to the source of a P-channel MOSFET 106 whose drain is connected to the base of an NPN bipolar transistor 110 for charging the load. The absolute value of the threshold voltage 106 of the P-channel MOSFET is set to a value larger than the absolute value of the threshold voltage of the other P-channel MOSFET 112 for constituting the CMOS circuits 112 and 113 on the same substrate.

7. 发明专利

JPH1027481A SEMICONDUCTOR INTEGRATED CIRCUIT 失效
公开(公告)号：JPH1027481A
公开(公告)日：1998-01-27
申请号：JP18236096
申请日：1996-07-11
申请人： HITACHI LTD
发明人： HIGUCHI HISAYUKI , SUZUKI MAKOTO , MIZUNO HIROYUKI , ISHIBASHI KOICHIRO , TACHIBANA MASARU , UEHARA KEIJIRO
IPC分类号： G11C11/41 , G06F12/10 , G11C11/14 , G11C11/419 , G11C15/04
摘要： PROBLEM TO BE SOLVED: To increase the operation speed for detecting coincidence of a associative memory device. SOLUTION: A CAM cell 23 is connected to a coincidence detecting line 25 through a NMOS 26, a coincidence detecting circuit 73 is connected to this coincidence detecting signal line 25 and has an accelerating circuit 356 and a differential amplifier circuit 32. The accelerating circuit 356 boosts rapidly a potential of the coincidence detecting signal line 25 to near the reference potential VR at the start of coincidence detection of data, after all NMOS 26 connecting plural memory cells and the line 25 are turned off because of that all of a plurality of memory cells connected to this line output a coincidence detecting signal, a potential of the coincidence detecting signal line 25 is boosted to a higher potential than the reference voltage VR, also after at least one of these NMOS 26 is turned on because of that at least one of these memory cells outputs a non-coincidence detecting signal, a current making a potential of the coincidence detecting signal line 25 lower than the reference voltage VR is supplied to the coincidence detecting signal line 25.

8. 发明专利

JPH08161862A MAGNETIC STORAGE DEVICE 失效
公开(公告)号：JPH08161862A
公开(公告)日：1996-06-21
申请号：JP30334594
申请日：1994-12-07
申请人： HITACHI LTD
发明人： TAKANO KOJI , KATO YASUHIRO , SHIROISHI YOSHIHIRO , SUZUKI MAKOTO , YOSHIDA TAKASHI , NISHIDA HIROSHI , SAITO AKIRA
IPC分类号： G11B25/04 , G11B20/00 , G11B33/12
摘要： PURPOSE: To obtain the device to be portable with good handleability and extensibility and high reliability by portably constituting an information storage part including a magnetic disk, its rotation drive part and an actuator, etc., and a circuit part including their control circuits and circuit boards, etc., in separated bodies. CONSTITUTION: A magnetic disk device consists of an information recording part and a circuit part constituted in a case having 3.3mm thickness, 54mm width and 106.8mm length. The storage part and the circuit part are both independently portable respectively, each have their connectors corresponding to PCMCIA, and one sheet of disk can be inserted to a PCMCIA type 1 slat, two sheets of disk to the type 2 and three sheets of disk to the type 3 at most. When a PDA is used as a computer main body, by inserting the information recording part and the circuit part into two PCMCIA type 1 slots provided in juxtaposition in a side of a PDA main body respectively, the magnetic disk device can be used as an external storage device of the PDA. Consequently, the thickness of the computer main body can be reduced to

9. 发明专利

JPH0779148A SEMICONDUCTOR INTEGRATED CIRCUIT 失效
公开(公告)号：JPH0779148A
公开(公告)日：1995-03-20
申请号：JP22168993
申请日：1993-09-07
申请人： HITACHI LTD
发明人： TACHIBANA MASARU , HIGUCHI HISAYUKI , SUZUKI MAKOTO , SASAKI KATSURO
IPC分类号： G11C11/413 , G11C11/407 , G11C11/417 , H03K19/017 , H03K19/0948
摘要： PURPOSE:To provide a circuit capable of operating at higher-speed than a conventional circuit by using an inexpensive CMOS technology. CONSTITUTION:Input signals 10, 11 and an output signal 30 are pulse signals, the gate width of PMOS 500, 501 and NMOS 100, 101 receiving the input signals 10, 11 at the gates is designed to be sufficiently smaller and a drain of a PMOS 600 whose gate width is designed to be sufficiently smaller is connected to an output and a power source, and a time-delayed signal in phase with an output signal is fed to a gate electrode 31. A potential 3 of sources of the PMOS 500, 501 is set lower than a power supply voltage Vcc 2 by nearly a threshold voltage Vth of the MOS transistors(TRs) or a potential 4 of a source of the NMOS 300 is set higher than a GND potential by nearly the Vth. Thus, the drive current of the load is increased almost twice and the delay time of the signal when the MOS 100, 101 are conductive is reduced.

10. 发明专利

JPH06314743A MANUFACTURE OF INTEGRATED CIRCUIT 失效
公开(公告)号：JPH06314743A
公开(公告)日：1994-11-08
申请号：JP22169793
申请日：1993-09-07
申请人： HITACHI LTD
发明人： OKUBO MICHIO , SUZUKI MAKOTO , SASAKI KATSURO , HONMA YOSHIO
IPC分类号： H01L21/82 , H01L21/66
摘要： PURPOSE:To replace a defective block with a non-defective block dispensing with a block selecting circuit and to improve an integrated circuit in yield by a method wherein a temporary wiring is removed after various blocks are tested, and an actual wiring is formed. CONSTITUTION:Semiconductor elements such as MOS transistors which form circuit blocks are manufactured in a first process 1 through conventional integrated circuit manufacturing treatments such as photolithography, impurity diffusion, ion implantation, and the like, and circuit blocks are connected together through a temporary wiring (one or more layers of conductor wiring) in a second process 2. The circuit blocks are subjected to a performance test in a third process 3, the temporary wiring is removed in a fourth process 4, and only normal circuit blocks are connected together through an actual wiring (one or more layers of conductor wiring) in a fifth process 5 avoiding defective blocks found in a block operation test. Therefore, an integrated circuit, can be improved in yield without increasing it in scale and operating delay time.

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