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21. 发明专利

JP2001117666A NONINTEGER FREQUENCY DIVIDING DEVICE 失效
公开(公告)号：JP2001117666A
公开(公告)日：2001-04-27
申请号：JP2000102304
申请日：2000-04-04
申请人： ISEI DENSHI KOFUN YUGENKOSHI
发明人： LEE SHAN-SHAN , RIN SHIHO
IPC分类号： G06F1/08 , G06F1/04 , H03K5/00 , H03K5/13 , H03K5/26 , H03K23/42 , H03K23/54 , H03K23/68
摘要： PROBLEM TO BE SOLVED: To allow the phase synchronizing loop of a motherboard to obtain various clock frequencies by using a relatively low 400 MHz clock signal. SOLUTION: Plural input clock signals, whose frequencies are the same, are converted into a target clock signals, and the m cycles of the input clock signals are made equal to the n cycles of the target clock signal by using a noninteger frequency dividing device. Then, plural edge trigger signals are generated from the input clock signals, and the cycles of the edge trigger signals are made equal to the 2m cycles of the input clock signals, and the rising edge and falling edge of any edge trigger signal is turned to the rising edge and falling edge of one of the input clock signals by using the noninteger frequency dividing devise. Then, a clock signal synthesizing circuit is connected with the clock signal edge trigger generating circuits, and the target clock signal can be synthesized from the edge trigger signals.

22. 发明专利

JPH11330951A COUNTER CIRCUIT 失效
公开(公告)号：JPH11330951A
公开(公告)日：1999-11-30
申请号：JP13833398
申请日：1998-05-20
申请人： MITSUBISHI ELECTRIC CORP
发明人： NAGURA TORU , UEDA KIMIHIRO
IPC分类号： H03K23/40 , H03K21/08 , H03K23/54
摘要： PROBLEM TO BE SOLVED: To obtain the counter circuit which generates no noise when operating. SOLUTION: Three stages of D flip-flops FF1 to FF3 are connected in series. A delay element 11 outputs a delayed signal S2D by delaying the signal S3 from the Q output of the D flip-flop FF1 by a delay time d2 and a delay element 12 outputs a delayed signal S3D by delaying the signal S3 from the Q output of the D flip-flop FF2 by a delay time d3. Here, the delay times d2 and d3 and a clock cycle Tc are so related that Tc>d2>d3. A 3-input NOR gate G1 receives the delayed signals S2D, S3D, and S4 (Q output of D flip-flop FF3), NORs those signals S2D, S3D, and S4, and outputs a signal S1 to the D input of the D flip-flop FF1.

23. 发明专利

JP2690516B2 失效
公开(公告)号：JP2690516B2
公开(公告)日：1997-12-10
申请号：JP20582688
申请日：1988-08-18
IPC分类号： G11C19/00 , H03K23/54

24. 发明专利

JPH09297189A CLOCKING CIRCUIT AND PULSE SIGNAL GENERATING METHOD 失效
公开(公告)号：JPH09297189A
公开(公告)日：1997-11-18
申请号：JP2865597
申请日：1997-02-13
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： TERADA YUTAKA , KUSUMOTO KEIICHI , MATSUZAWA AKIRA
IPC分类号： G04F10/04 , G06F1/10 , H03K23/00 , H03K23/54 , H03L7/099
摘要： PROBLEM TO BE SOLVED: To provide a clocking circuit of high clocking accuracy, low power consumption and a small circuit scale. SOLUTION: A differential inverter ring 11 is constituted by connecting normal rotation output terminals and reverse rotation input terminals, and reverse rotation output terminals and normal rotation input terminals of the odd number of differential inverters of the same constitution, and the transition of signals is circulated by oscillation. A first signal group formed of the odd- numbered stages of normal rotation output signals and the even-numbered stages of reverse rotation output signals inputted to a first holding circuit row 12 rises or falls in order with delay time as time intervals. In the same way, a second signal group inputted to a second holding circuit row 13 also rises or fails in order at fixed time intervals. Clocking therefore becomes constant even with the difference between the rising time and falling time of the output signals of the respective differential inverters constituting the differential inverter ring 11.

25. 发明专利

JPH09232945A FREQUENCY DIVIDER, RING COUNTER AND PLL CIRCUIT 失效
公开(公告)号：JPH09232945A
公开(公告)日：1997-09-05
申请号：JP3827096
申请日：1996-02-26
申请人： FUJITSU LTD
发明人： NAITO HIDETOSHI , KUBOTA MIKI , AIZAWA KATSUAKI
IPC分类号： H03K23/54 , H03L7/08 , H03L7/18
摘要： PROBLEM TO BE SOLVED: To prevent problems attended with production of incorrect duty pulses while correcting a phase deviation of a frequency divider by applying logic arithmetic operation to an output of a flip-flop and an output of a latch element and outputting the result as a frequency division clock. SOLUTION: A clock CK is given to a D FF 11 and a phase control signal P is given to a latch element 12 simultaneously. The clock CK is frequency- divided by 2 with the FF 11 and the resulting clock signal is given to one input of an EX-OR element 13. Simultaneously the latched signal P is outputted synchronously with the rising of the clock CK. An output of the element 12 and an output of the FF 11 are given to the element 13, in which the clock CK is frequency-divided by 2 into a division clock CK/2. In this case, at need, a level of the signal P is switched, e.g. from '0' to '1', the output logic of the element 13 is inverted and a prescribed phase is obtained.

26. 发明专利

JP2621268B2 失效
公开(公告)号：JP2621268B2
公开(公告)日：1997-06-18
申请号：JP32759787
申请日：1987-12-24
IPC分类号： H03K23/54 , H03K23/64

27. 发明专利

JPH08321775A FREQUENCY DIVIDER 失效
公开(公告)号：JPH08321775A
公开(公告)日：1996-12-03
申请号：JP14966195
申请日：1995-05-24
申请人： HEWLETT PACKARD JAPAN LTD
发明人： KOMATSU YASUAKI , YANAGIMOTO YOSHIYUKI
IPC分类号： H03L7/183 , H03K23/00 , H03K23/54 , H03K23/68 , H03L7/197
摘要： PURPOSE: To obtain the frequency divider with decimal fraction in which switchover and setting of a frequency division ratio are conducted at a high speed in order to reduce phase noise of a frequency synthesizer so as to increase a response speed. CONSTITUTION: The frequency divider (frequency divider with decimal fraction) conducting frequency division of a frequency division ratio including a decimal fraction is provided with a pre-stage frequency divider means 2 setting plural integer frequency division ratio, a post-stage frequency divider means (shift register) 4A, a bit selector 13A, a CA value generator 11 and a ΣΔ modulator 10. The setting of the frequency division ratio of the pre-stage frequency divider means 2, a period of a frequency division output signal, a frequency division ratio of the post-stage frequency divider is switched to attain frequency division with a decimal fraction. A shift register is employed for the post-stage frequency divider means without adoption of a programmable counter at a slow speed to attain a fast setting changeover speed.

28. 发明专利

JP2555978B2 失效
公开(公告)号：JP2555978B2
公开(公告)日：1996-11-20
申请号：JP11487994
申请日：1994-05-27
申请人： NIPPON ELECTRIC CO
发明人： YAMAMOTO NAONOBU
IPC分类号： H03K23/48 , H03K23/54 , H03K23/64 , H03K23/70

29. 发明专利

JPH07321642A FREQUENCY DIVIDER CIRCUIT 失效
公开(公告)号：JPH07321642A
公开(公告)日：1995-12-08
申请号：JP11487994
申请日：1994-05-27
申请人： NEC CORP
发明人： YAMAMOTO NAONOBU
IPC分类号： H03K23/48 , H03K23/54 , H03K23/64 , H03K23/70
摘要： PURPOSE:To provide an odd number frequency divider circuit simple in circuit configuration, easy to change a frequency division ratio and capable of obtaining the output of duty factor of 50%. CONSTITUTION:A master clock noninverting signal is given to each clock input CIN of odd number stages of flip-flops 11 of 2N-sets each in which data output Q of a pre-stage are given to a data input D of a post-stage and a data inverting output QB at a final stage is given to a data input D of a 1st stage and a master clock inverting signal is given to even number stages of flip-flops to form N-stages of Jhonson counters. Each data output of an N-th stage flip- flop and a 2N-th stage of flip-flop is given to an AND gate 13 and each data inverting output is given to an AND gate 14, in which data are ANDed. When the ANDed data are given to an OR gate 15, an output signal whose duty factor is 50% resulting from applying 1/N frequency division to a master clock is obtained.

30. 发明专利

JPH0630442B2 失效
公开(公告)号：JPH0630442B2
公开(公告)日：1994-04-20
申请号：JP19944587
申请日：1987-08-10
申请人： FUJITSU LTD
发明人： KOSUGI TOORU , FURUKAWA TAKAHIRO
IPC分类号： H03K23/54

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