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1. 发明专利

JP3703347B2 Divider circuit 有权
公开(公告)号：JP3703347B2
公开(公告)日：2005-10-05
申请号：JP30718299
申请日：1999-10-28
申请人：アイコム株式会社
发明人：紀佳桜井
IPC分类号： H03K21/10 , H03K23/68 , H03K23/70

2. 发明专利

JP3633299B2 Divider 有权
公开(公告)号：JP3633299B2
公开(公告)日：2005-03-30
申请号：JP22139998
申请日：1998-08-05
申请人：松下電器産業株式会社
发明人：真中村 , 佳代中西 , 幸生平岡
IPC分类号： H03K23/66 , H03K23/70

3. 发明专利

JP2555978B2 失效
公开(公告)号：JP2555978B2
公开(公告)日：1996-11-20
申请号：JP11487994
申请日：1994-05-27
申请人： NIPPON ELECTRIC CO
发明人： YAMAMOTO NAONOBU
IPC分类号： H03K23/48 , H03K23/54 , H03K23/64 , H03K23/70

4. 发明专利

JPH07321642A FREQUENCY DIVIDER CIRCUIT 失效
公开(公告)号：JPH07321642A
公开(公告)日：1995-12-08
申请号：JP11487994
申请日：1994-05-27
申请人： NEC CORP
发明人： YAMAMOTO NAONOBU
IPC分类号： H03K23/48 , H03K23/54 , H03K23/64 , H03K23/70
摘要： PURPOSE:To provide an odd number frequency divider circuit simple in circuit configuration, easy to change a frequency division ratio and capable of obtaining the output of duty factor of 50%. CONSTITUTION:A master clock noninverting signal is given to each clock input CIN of odd number stages of flip-flops 11 of 2N-sets each in which data output Q of a pre-stage are given to a data input D of a post-stage and a data inverting output QB at a final stage is given to a data input D of a 1st stage and a master clock inverting signal is given to even number stages of flip-flops to form N-stages of Jhonson counters. Each data output of an N-th stage flip- flop and a 2N-th stage of flip-flop is given to an AND gate 13 and each data inverting output is given to an AND gate 14, in which data are ANDed. When the ANDed data are given to an OR gate 15, an output signal whose duty factor is 50% resulting from applying 1/N frequency division to a master clock is obtained.

5. 发明专利

JPH03126116A METHOD OF GENERATING CLOCK OF I/O CARD OF PERSONAL COMPUTER 失效
公开(公告)号：JPH03126116A
公开(公告)日：1991-05-29
申请号：JP26085189
申请日：1989-10-05
申请人： KAHOU DENSHI KOFUN YUUGENKOUSH
发明人： HAYASHI CHIKAMOTO , HOU BUNKIN , SOU IYUU , YOU YOUSHIYOU
IPC分类号： G06F1/10 , H03K23/70
摘要： PURPOSE: To eliminate the need of an independent crystal oscillator and to reduce the cost by inputting a main board clock from a personal computer, processing the main board clock and making it into a control clock having a frequency which is preset. CONSTITUTION: An I/O card 30 is provided with a connector 31 inserted into the slot of a main board in the personal computer, a UART (general-purpose asynchronous transmitter/receiver) circuit 32 receiving and transmitting a data bit and a frequency division circuit 33, The clock is directly impressed on the I/O card 30 from the main board of the personal computer. The clock of the main board is processed into the desired clock for UART circuit 32 of the I/O card 30 in the division circuit 33. The desired clock is inputted to the UART circuit 32 of the I/O card 30. Thus, the clock in the I/O card 30 can be generated without using the independent crystal oscillator.

6. 发明专利

JPS62265815A DUTY CONVERTING CIRCUIT 失效
公开(公告)号：JPS62265815A
公开(公告)日：1987-11-18
申请号：JP11131386
申请日：1986-05-13
申请人： MITSUBISHI ELECTRIC CORP
发明人： KAWASHIMA HIKARI
IPC分类号： H03K23/00 , H03K5/04 , H03K21/02 , H03K23/70
摘要： PURPOSE:To convert an input pulse into a pulse whise duty is 1:1 without causing malfunction by using an inverter to invert an input pulse, ANDing an output of a 1/(2n+1) frequency division circuit and an inverter output so as to set or reset a shift register. CONSTITUTION:A 1/3 frequency division circuit 20 applies 1/3 frequency division to an input pulse (a) to output a pulse (b) whose duty is 1:2 synchronously with the positive leading edge of the input pulse (a) from an output terminal Q1. An AND circuit 4 ANDs the output of the 1/3 frequency division circuit 20 and the output of the inverter 3, outputs a pulse C, which is given to a set terminal S of a shift register 5. The shift register 5 shifts the output of the 1/3 frequency division circuit 20 for one period of the input pulse (a) synchronously with the positive leading edge of the input pulse (a), and since the output of the AND circuit 4 is given to the set terminal S of the shift register 5, a pulse (d) whose frequency is 1/3 of the frequency of the input pulse (a) and whose duty is 1:1 is outputted from the output terminal Q2 of the shift register 5.

7. 发明专利

JPS6062240A FREQUENCY DIVIDING CIRCUIT 失效
公开(公告)号：JPS6062240A
公开(公告)日：1985-04-10
申请号：JP16845983
申请日：1983-09-14
申请人： NIPPON TELEGRAPH & TELEPHONE
发明人： TAJIMA ATSUSHI
IPC分类号： H03K23/58 , H03K23/70
摘要： PURPOSE:To obtain the 1/(n-1) or 1(n+1) frequency divided output signal of an external input signal by connecting the output of a 1/n frequency divider to a frequency dividing circuit output terminal, and feeding the output signal back to one of anolog multipliers. CONSTITUTION:The external input signal from an external input terminal 6 is inputted to one input terminal of an analog multiplier 8, and the output of the 1/n frequency divider 10 is inputted to the other input terminal 13 of the multiplier 8. When input signal frequencies at terminals 12 and 13 are fa and fb respectively, the output signal of the multiplier 8 contains frequency components fa+fb and fa-fb. When the component fa-fb passes through BPF9, the frequency divider 10 outputs the 1/n-frequency output to an output terminal 7 and also feeds it back to the multiplier 8. Thus, a 1/(n+1) frequency divider is obtained. When the component fa+fb passes through the BPF9, on the other hand, a 1/(n-1) frequency divider is obtained similarly.

8. 发明专利

JP2009524319A Frequency divider circuit 有权
公开(公告)号：JP2009524319A
公开(公告)日：2009-06-25
申请号：JP2008550855
申请日：2007-01-15
申请人：フューチャーウェイブズユーケーリミテッドFuture Waves UK Limited
发明人：ミラー，ロビン，ジェームズ
IPC分类号： H03K23/48 , H03K23/54 , H03K23/66 , H03K23/70
CPC分类号： H03K23/544 , G06F1/3203 , G06F1/3287 , H03F3/189 , H03F3/45188 , H03F2200/294 , H03F2200/372 , H03F2200/489 , H03F2200/492 , Y02D10/126 , Y02D10/171
摘要：入力クロック信号の周波数のＮ分の１（Ｎは奇数）である周波数を有する出力クロック信号を、入力クロック信号から得るための回路である。回路は、ラッチリングとして構成される複数のラッチを有する。ラッチは連続する対に配置され、各ラッチ対は、入力クロック信号の立ち上がりまたは立ち下がりエッジのいずれか一方でオンに切り替わる第１のラッチと、入力クロック信号の立ち上がりまたは立ち下がりエッジのいずれか他方でオンに切り替わる第２のラッチとを備える。ＲＳフリップフロップは、立ち上がりエッジでオンに切り替わるラッチリングからの出力をセットおよびリセット入力のいずれか一方で受信し、かつ立ち下がりエッジでオンに切り替わるラッチリングからの出力をセットおよびリセット入力のいずれか他方で受信するように連結される。前記出力クロック信号はＲＳフリップフロップの出力に供給される。

9. 发明专利

JPH0964725A ODD NUMBER FREQUENCY DIVIDER CIRCUIT 失效
公开(公告)号：JPH0964725A
公开(公告)日：1997-03-07
申请号：JP21918295
申请日：1995-08-28
申请人： MATSUSHITA ELECTRIC WORKS LTD
发明人： NAKAMURA HIDEKI , YABUTA AKIRA , ITO HISAHARU , OKITA ATSUSHI
IPC分类号： H03K23/66 , H03K23/70
摘要： PROBLEM TO BE SOLVED: To realize the structure of the odd number frequency divider circuit in which a duty cycle of a frequency division output is 1:1. SOLUTION: The circuit is provided with a counter 2 whose output Q2 connects to its reset input R and having outputs Q0-Q3 in 4 bit width, a D flip-flop 3 receiving an output of the output Q1 of the counter 2 at its data input D and receiving a clock signal at a clock input CLK via a NOT circuit 4, and an OR circuit 5 ORing an output signal outputted from the output Q of the D flip-flop 3 and a signal outputted from the output Q1 of the counter 2.

10. 发明专利

JPS6376617A ODD NUMBER FREQUENCY-DIVIDING CIRCUIT 失效
公开(公告)号：JPS6376617A
公开(公告)日：1988-04-06
申请号：JP22233586
申请日：1986-09-19
申请人： FUJITSU LTD
发明人： OKADA KIMIYOSHI
IPC分类号： H03K23/00 , H03K23/70
摘要： PURPOSE:To obtain a circuit suitable for forming an LSI by obtaining the OR of the odd number frequency-dividing clock obtained by odd-number- frequency-dividing an input clock and the clock to half-bit-shift the odd number frequency-dividing clock with a D type flip-flop into which a phase-reversal clock is inputted, when the odd number frequency-dividing clock is obtained. CONSTITUTION:The output of an odd number frequency-dividing means and the output of a D type flip-flop 4, to which a phase-reversal clock is inputted in order to half-bit-shift an odd number frequency-dividing means output are constituted to be added to an OR circuit 5. Namely, for an odd number frequency-dividing clock from the odd number frequency-dividing means 1 and the clock to half-bit-shift the odd number frequency-dividing clock with a phase- reversal clock by the D type flip-flop 4, the OR is obtained by an OR means 5 and the odd number frequency-dividing clock of a duty factor 50% is obtained. Thus, by miniaturizing and decreasing an adjusting place, a circuit constitution suitable to forming an LSI is obtained.

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