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1. 发明专利

JPH0746238A ROUTING NETWORK MONITOR SYSTEM 失效
公开(公告)号：JPH0746238A
公开(公告)日：1995-02-14
申请号：JP17963693
申请日：1993-07-21
申请人： FUJITSU LTD , NIPPON TELEGRAPH & TELEPHONE
发明人： TAKIZAWA YUJI , KAWAI MASAAKI , NAITO HIDETOSHI , TAJIMA KAZUYUKI , IKEDA TOSHIMI , YAMASHITA HARUO , AKUTSU KENJI , UEDA HIROMI
IPC分类号： H04L12/24 , H04L12/26 , H04L12/70 , H04L12/701 , H04L12/56
摘要： PURPOSE:To obtain the routing network monitor system attended with confirmation of a real passing path of a packet with respect to the routing network monitor system. CONSTITUTION:The system is provided with a monitor control section 2 inserting a path check packet and recovering the packet to a routing network 1 and with a path monitor section 3 provided to each path in the routing network 1 and providing passing location information corresponding to the path check packet passing through each path and the monitor control section 2 monitors the actual passing state of the routing network 1 based on passing position information of the path check packet to be recovered. Preferably, the monitor control section 2 compares the schedule information of a known path with the passing location information of a recovered packet to monitor the state of the routing network 1. Furthermore, the path monitor section 3 is provided with a comparison section comparing the schedule information of the path added to the path check packet with the passing location information of the path monitor section 3 and outputs an alarm signal to the monitor control section 2 when the coincidence of the comparison is not obtained.

2. 发明专利

JPH05324121A CLOCK DISTRIBUTING CIRCUIT 失效
公开(公告)号：JPH05324121A
公开(公告)日：1993-12-07
申请号：JP12589892
申请日：1992-05-19
申请人： FUJITSU LTD
发明人： KAWAI MASAAKI , NAITO HIDETOSHI , TAKIZAWA YUJI , TAJIMA KAZUYUKI , IKEDA TOSHIMI , SATO HIROYUKI
IPC分类号： G06F1/10 , H03H7/48
摘要： PURPOSE:To obtain a simple circuit constitution without requiring a DC connection circuit by connecting a capacity connecting capacitor to the post stage of a branching part for branching a single clock outputted from a DC clock source into plural clocks. CONSTITUTION:A branching part 2 branches an output signal line from a DC clock source 1 into plural lines and is connected to respective terminal resistors 3 through respective output side capacitors 5. Namely a single clock from the DC clock source 1 is branched into plural clocks and the branched clocks are passed through the capacity connecting capacitors 5, so that DC components are cut out from respective clocks and AC clocks are applied to the resistors 3. Since each terminal resistor 3 does not require the execution of termination by an ECL gate circuit like a convensional method and attains its function by considering only impedance matching, useless power consumption due to the combination of the unnecessary ECL gate circuit and the terminal resistor can be reduced.

3. 发明专利

JPH04216215A IC CIRCUIT 失效
公开(公告)号：JPH04216215A
公开(公告)日：1992-08-06
申请号：JP41097290
申请日：1990-12-14
申请人： FUJITSU LTD
发明人： NAITO HIDETOSHI , OTSUKA TOMOYUKI
IPC分类号： H03K19/003 , H03K19/086
摘要： PURPOSE:To generate an output signal whose duty ratio is equal to that of an input signal even when the temperature/power supply voltage fluctuation characteristic of a reference voltage generation part is not coincident to that of the IC circuit in a preceding step. CONSTITUTION:The output signal of the preceding step IC circuit is applied to a following step IC circuit 1 as an input signal Cin after removing the DC component by a direct current component removing means 3. At such a time, a reference voltage Vref is applied from a reference voltage generation part 2 to a reference voltage terminal and applied through a bias means 4 to the input signal Cin as a bias voltage. Therefore, by applying the reference signal Vref as an average value bias to the signal after removing the direct current component, this bias voltage has no relation to the preceding step IC circuit and accordingly, the average value of a waveform is positioned at a center.

4. 发明专利

JPH02285715A FREQUENCY DIVISION CIRCUIT 失效
公开(公告)号：JPH02285715A
公开(公告)日：1990-11-26
申请号：JP10691189
申请日：1989-04-26
申请人： FUJITSU LTD
发明人： NAITO HIDETOSHI , OTSUKA TOMOYUKI , KAWAI MASAAKI , TANIGUCHI MITSUKI
IPC分类号： H03K23/00
摘要： PURPOSE:To control the phase of a frequency division clock by providing plural inverting means connecting to a pre-stage or post-stage of plural FFs connected in series, and inverting the phase of an input output signal in response to a control signal. CONSTITUTION:An input clock signal is inputted to a DFF 321 via an OR gate 311 being an inverting means and frequency-divided by 1/2. The frequency division output is inputted to a DFF 323 via an OR gate 313 being an inverting means of the next stage, and the further frequency-divided by 1/2. A logic level of a signal supplied from a control terminal P0 is switched to invert the phase of the clock signal supplied to the DFF 321, then a frequency division clock signal synchronously with the trailing edge of the input signal with a phase delay of 45 deg. is obtained from an output terminal Q of the DFF 323. Moreover, the logic level of the signal supplied from a control terminal P1 is switched to obtain a 1/4 frequency division clock signal whose phase is delayed by 90 deg..

5. 发明专利

JPH02246615A GATE CIRCUIT 失效
公开(公告)号：JPH02246615A
公开(公告)日：1990-10-02
申请号：JP6811489
申请日：1989-03-20
申请人： FUJITSU LTD
发明人： NAITO HIDETOSHI , OTSUKA TOMOYUKI
IPC分类号： H03K19/0952
摘要： PURPOSE:To attain stable high speed operation by connecting a component to a 2nd differential pair, adjusting a level of the component having between its terminals corresponding to a 1st differential pair to make the load state of two transistors(TRs) of the 2nd differential pair equal to each other. CONSTITUTION:Two FETs 211, 213 forming a 1st differential pair, two FETs 221, 223 forming a 2nd differential pair, a FET 231 acting like a constant current source, two resistors 241, 243 acting like a load resistor, a resistor 261 for load adjustment and a diode 251 are provided to the gate circuit. The resistance of the resistor 261 is set to cause a voltage drop equal to a source- drain voltage of the FET 213 or the FET 211 in the operating state when the PET 233 is in the operating state. Thus, the load state of the FETs 221, 223 is made equal, hence stable high speed operation is realized.

6. 发明专利

JPS6460035A BRANCHING/INSERTING CIRCUIT 失效
公开(公告)号：JPS6460035A
公开(公告)日：1989-03-07
申请号：JP21509587
申请日：1987-08-31
申请人： FUJITSU LTD
发明人： TANIGUCHI MITSUKI , OTSUKA TOMOYUKI , NAITO HIDETOSHI , KONDO RYUICHI
IPC分类号： H04J3/08 , H04Q11/04
摘要： PURPOSE:To reduce the scale of the titled circuit by sharing a part of the circuit between a branching circuit and a inserting circuit. CONSTITUTION:Second clock signals with low frequencies given to second latch circuits 3-1-3-n, which constitute a separating circuit, are also given to data insertion selecting switches 5-1-5-n. That is, second clock signals f/n are sent through the data insertion selecting switches 5-1-5-n, which are turned on, to switches 2-1-2-n for data insertion respectively corresponding to the signals f/n, and thus, bits corresponding to the data or f/n bit/second are inserted to latch circuits 1-1-1-(n+1) respectively corresponding to the data, and the data of f/n bit/second are branched from second latch circuits 3-1-3-n. Thus, the circuit scale can be reduced and the control of the branching and insertion can be simplified.

7. 发明专利

JPS63156417A FET SWITCHING CIRCUIT 失效
公开(公告)号：JPS63156417A
公开(公告)日：1988-06-29
申请号：JP30448586
申请日：1986-12-19
申请人： FUJITSU LTD
发明人： NAITO HIDETOSHI , OTSUKA TOMOYUKI , TANIGUCHI MITSUKI , KONDO RYUICHI
IPC分类号： H03K17/10 , H03K17/687
摘要： PURPOSE:To realize the high voltage of the output voltage of a FET switching circuit and to stabilize switching, by connecting a FET in series between a drain voltage supplying terminal and a source voltage supplying terminal. CONSTITUTION:In a case that two GaAsFETs are used, and a switching drive input voltage is supplied to the gate input at every FET, and when a voltage V1 having a value smaller than the sum of the half value of a drain voltage VDD supplied to the drain voltage supplying terminal 3 and a pinch off voltage Vp is supplied to a drive input terminal 71, and a V2 lower by the Vp is supplied to the drive input terminal 71, the FETs 61 and 62 go to cut off states, and when the V2 is higher than the Vp, the FETs 61 and 62 are energized. In such way, it is possible to use the VDD higher than ever even when the allowable voltages of the FETs are same, and to obtain the high voltage of the switching voltage.

8. 发明专利

JPH10290130A DIFFERENTIAL AMPLIFIER CIRCUIT 失效
公开(公告)号：JPH10290130A
公开(公告)日：1998-10-27
申请号：JP9911997
申请日：1997-04-16
申请人： FUJITSU LTD
发明人： NAITO HIDETOSHI
IPC分类号： H03F3/45
摘要： PROBLEM TO BE SOLVED: To exactly match the frequency characteristics of a pair of complementary signals by inserting inductors to the respective drain loads of a pair of FETs at a differential transistor part for comparing an input signal with a reference voltage at a differential amplifier circuit having the differential transistor part and a source follower part for outputting a pair of complementary signals corresponding to the compared result. SOLUTION: Inductors 15 and 16 are inserted to the drain loads of a pair of FET 4 and 5 consisting of a differential transistor part 3a and the values of inductors 15 and 16 are adjusted so that the frequency characteristics of a pair of complementary signals Q and XQ outputted from a source follower part 6 can be matched. Namely, by setting the value of inductor 16 on the side of A larger than the value of inductor 15 on the side of XQ, the frequency characteristics of Q are shifted to the side of high frequency without shifting the frequency characteristics of XQ to the side of low frequency and both the characteristics are matched. Thus, the amplitude of Q can be matched with that of XQ.

9. 发明专利

JP2530368B2 失效
公开(公告)号：JP2530368B2
公开(公告)日：1996-09-04
申请号：JP9704089
申请日：1989-04-17
申请人： FUJITSU LTD
发明人： NAITO HIDETOSHI , OOTSUKA TOMOYUKI , KAWAI MASAAKI , KONDO RYUICHI
IPC分类号： H01L33/00

10. 发明专利

JPH0766787A POINTER ABNORMALITY DETECTING SYSTEM 失效
公开(公告)号：JPH0766787A
公开(公告)日：1995-03-10
申请号：JP20760993
申请日：1993-08-23
申请人： FUJITSU LTD , NIPPON TELEGRAPH & TELEPHONE
发明人： NAITO HIDETOSHI , KAWAI MASAAKI , TAKIZAWA YUJI , TAJIMA KAZUYUKI , IKEDA TOSHIMI , SATO HIROYUKI , UEMATSU HITOSHI , UEDA HIROMI
IPC分类号： H04J3/14 , H04J3/00 , H04L1/00
摘要： PURPOSE:To provide a pointer abnormality detecting system capable of effectively detecting the abnormality of an AU-4-Nc pointer by simple constitution. CONSTITUTION:A pointer abnormality detecting system for detecting the abnormality of the AU-4-Nc pointer at the time of receiving an STM-N frame in synchronous digital hierarchy transmission is provided with a detecting means 10 for detecting discrepancy by comparing respective data of the received AU-4-Nc pointer with respective data stored in itself and a judging means 20 for judging the abnormality of the pointer when the means 10 detects any one or more coincidence continuously > n frames. Preferably respective data of H1#2/H1#3N bytes and H2#2/H2#3N bytes are fixed.

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