PROBLEM TO BE SOLVED: To prevent problems attended with production of incorrect duty pulses while correcting a phase deviation of a frequency divider by applying logic arithmetic operation to an output of a flip-flop and an output of a latch element and outputting the result as a frequency division clock. SOLUTION: A clock CK is given to a D FF 11 and a phase control signal P is given to a latch element 12 simultaneously. The clock CK is frequency- divided by 2 with the FF 11 and the resulting clock signal is given to one input of an EX-OR element 13. Simultaneously the latched signal P is outputted synchronously with the rising of the clock CK. An output of the element 12 and an output of the FF 11 are given to the element 13, in which the clock CK is frequency-divided by 2 into a division clock CK/2. In this case, at need, a level of the signal P is switched, e.g. from '0' to '1', the output logic of the element 13 is inverted and a prescribed phase is obtained.