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21. 发明专利

JPH06348590A MAIN STORAGE DEVICE AND MEMORY CARD 失效
公开(公告)号：JPH06348590A
公开(公告)日：1994-12-22
申请号：JP13755293
申请日：1993-06-08
申请人： HITACHI LTD , HITACHI COMPUTER ENG
发明人： MIURA SHUICHI , KUROSAWA KENICHI , ISHIKAWA SUKETAKA , FUKUNAKA HIDETADA , NAGAI EIICHIRO
IPC分类号： G06F12/06
摘要： PURPOSE:To provide a main storage device of a small-sized computer such as a work station with nearly the same performance as the main storage device of a large-sized computer with a small physical quantity. CONSTITUTION:Plural storage parts (1-A0-1-A3, and 1-B0-1-B3) are constituted by providing with four groups of storage parts made of a couple of two storage parts (1-A0, 1-B0...), and the data lines of the couples of respective storage parts are made common and connected to a data part 4. A host computer 4 sends a request to access the main storage device to a control part 2. The control part 2 receives the access request and activates a storage part 1 through a control signal 2000-A or 2000-B. The control signal 2000-A activates the storage parts 1-A0-1-A3 and the control signal 2000-B activates the storage parts 1-B0-1-B3. Data read out of the storage parts 1-A0 and 1-B0 are inputted to the data part 3 through a common data line 3000-0 and the data part 3 switches the read data coming from the respective data lines 3000-0, 3000-1...3000-3 in order and transfers them to the host computer 4 through a data line 4000.

22. 发明专利

JPH06161623A NOISE COUNTERMEASURE INTERFACE CIRCUIT 失效
公开(公告)号：JPH06161623A
公开(公告)日：1994-06-10
申请号：JP31173292
申请日：1992-11-20
申请人： HITACHI LTD
发明人： FUKUNAKA HIDETADA , ISHIKAWA SUKETAKA , FUKUDA KIMIO , NAKAJIMA KENJI
IPC分类号： G06F3/00
摘要： PURPOSE:To eliminate the effect of noise on adjacent output pins by invalidating the transmission of the output signal which is adjacent to an output data bus for only the period when the output level of this output data bus is inverted and controlling to retransmit it after the elapse of an inversion period. CONSTITUTION:The level inversion of the preliminarily fixed bits of output data buses of LSI pins are successively outputted is detected by level inversion detection circuits 2a, 2b, 16. For only the period when the output level of the output data bus is inverted by the detection circuit 16, the transmission of the output signal of a B bus which is adjacent to the output data bus is invalidated. A B-bus valid flip flop 17 is controlled to retransmit the signal after the elapse of an inversion period. By this constitution, LSI reproducing cost can be reduced by eliminating the effect of noise on adjacent input pins or output pins without increasing the number of LSI pins.

23. 发明专利

JPH0319568B2 失效
公开(公告)号：JPH0319568B2
公开(公告)日：1991-03-15
申请号：JP16931984
申请日：1984-08-15
申请人： HITACHI LTD
发明人： ISHIKAWA SUKETAKA
IPC分类号： G06F7/50 , G06F7/02 , G06F7/508

24. 发明专利

JPH02294713A TOD COUNTING SIGNAL GENERATING CIRCUIT 失效
公开(公告)号：JPH02294713A
公开(公告)日：1990-12-05
申请号：JP11494589
申请日：1989-05-10
申请人： HITACHI LTD
发明人： YAMAGATA MAKOTO , ISHIKAWA SUKETAKA
IPC分类号： G06F1/14
摘要： PURPOSE:To obtain a group of counters whose updating time is completely the same by mutually transferring a synchronizing signal synchronized by a synchronizing circuit between its own system and the other system, and selecting and outputting a signal outputted first out of synchronizing signals from the self-system and the other system as a synchronizing signal for updating a TOD counter. CONSTITUTION:Both the systems are respectively provided with synchronizing circuits 12, 22 to be driven by a common clock 1, and time-of-day (DOD) count signal forming circuits 10, 20 which synchronizes synchronizing signals with nearly constant period sent from the other and its own systems and generates a synchronizing signal, are respectively provided with synchronizing signal sending circuits. The synchronizing signal sending circuits mutually send synchronized synchronizing signals and each of them selects and outputs a synchronized signal output first out of the synchronizing signals in the its own system and the other system as the updating signal of the TOD counter and updates the TOD counter by the updating signal. Consequently, even when a circuit has plural synchronizing circuits, their updating time can be allowed to coincide and all TOD values can always be allowed to coincide with each other.

25. 发明专利

JPH01269131A INSTRUCTION PRECEDENCE CONTROL SYSTEM 失效
公开(公告)号：JPH01269131A
公开(公告)日：1989-10-26
申请号：JP9749888
申请日：1988-04-20
申请人： HITACHI LTD
发明人： ISHIKAWA SUKETAKA
IPC分类号： G06F9/32 , G06F9/34 , G06F9/38
摘要： PURPOSE:To improve the performance of an instruction precedence control by calculating a branching address in a instruction processing cycle with the value of the special bit of the operand data shown by a mode setting branching instruction as an address mode set newly and executing the branching with the result, when the mode setting branching instruction is decoded. CONSTITUTION:In the precedence processing cycle of a BSM instruction and a BASSM instruction when a mode setting and an unconditional branching instruction (BSM instruction) and a mode setting unconditional branching linkage instruction (BASSM instruction) are executed, an address calculation is executed in accordance with the value shown by a bit-0 of a general purpose register in which an R2 field of the instruction is designated and with the calculated result as a branching destination address, the taking-out of the branching destination instruction is immediately activated. Thus, in the precedence processing cycle of the BSM instruction and the BASSM instruction, a desired branching destination address can be obtained and in the precedence processing cycle, the activation of the take-out of the branching destination instruction can be executed by the obtained branching destination address.

26. 发明专利

JPS6315619B2 失效
公开(公告)号：JPS6315619B2
公开(公告)日：1988-04-05
申请号：JP2323082
申请日：1982-02-16
申请人： HITACHI LTD
发明人： OOTSUKI TOORU , OOSHIMA YOSHIO , ISHIKAWA SUKETAKA , FUKUDA MASAHARU
IPC分类号： G06F7/491 , G06F7/493 , G06F7/496 , G06F7/508 , G06F7/52

27. 发明专利

JPS6148038A Zero detection of adder 失效
标题翻译：零检测添加剂
公开(公告)号：JPS6148038A
公开(公告)日：1986-03-08
申请号：JP16931984
申请日：1984-08-15
申请人： Hitachi Ltd
发明人： ISHIKAWA SUKETAKA
IPC分类号： G06F7/50 , G06F7/02 , G06F7/508
CPC分类号： G06F7/02
摘要： PURPOSE:To make possible a high-speed processing by detecting with separate means (complement on 1 or complement on 2) that an addition output is zero by the presence or absence of an initial carry. CONSTITUTION:When there is an initial carry, an output of a zero detection circuit (A)4 detecting that outputs of input control sections 1-a, 1-b are complements of 1 each other is ANDed at an AND gate 7. Then, through an OR gate 9, the result of the output of zero or not of an adder 2 is fed onto a zero detection line 13. When there is no initial carry, an output of a zero detection circuit (B)5 detecting that outputs of input control sections 1-a, 1-b are complements of 2 each other is ANDed at the AND gate 8. Then, through an OR gate, 9, the result of the output of zero or not of the adder 2 is fed onto the zero detection line 13.
摘要翻译：目的：通过用单独的手段（1或补码2）进行检测，通过初始进位的存在或不存在，加法输出为零可以实现高速处理。构成：当存在初始进位时，检测输入控制部1-a，1-b的输出的零检测电路（A）4的输出在“与”门7进行“与”运算。然后，通过或门9，将加法器2的输出0的结果输出到零检测线13上。当没有初始进位时，零检测电路（B）5的输出检测到输入控制部分1-a，1-b彼此互补，在与门8进行“与”运算。然后，通过“或”门9，将加法器2的输出0的结果输出到零检测线13。

28. 发明专利

JPS6011927A DECIMAL MULTIPLYING DEVICE 失效
公开(公告)号：JPS6011927A
公开(公告)日：1985-01-22
申请号：JP11955683
申请日：1983-07-01
申请人： HITACHI LTD
发明人： OOTSUKI TOORU , OOSHIMA YOSHIO , ISHIKAWA SUKETAKA , YABE HIDEAKI , FUKUDA MASAHARU
IPC分类号： G06F7/496 , G06F7/491 , G06F7/506 , G06F7/508 , G06F7/52 , G06F7/527
摘要： PURPOSE:To obtain a multiplying device which can perform a decimal loop addition at a high speed by using the double input of a 3-input carry save adder as the input of an intermediate product which is shown in the form of a carry and another input as the input of the product of a decimal part. CONSTITUTION:The double input of a 3-input carry save adder is used as the input of an intermediate product shown in the form of a carry, and another input is used as the input of the product of a decimal part. For instance, 6 is added every decimal digit by a 6-addition correcting circuit 28 as the initial setting to start the loop addition. Then the intermediate product held in the form of a sum and a carry is added with the product to a decimal part obtained by another arithmetic means by a 3-input carry save adder CSA29. Then the correction is given to the sum output as well as to an upper decimal digit from a sum output correction circuit 31 and a decimal upper digit corretion circuit 32 for each decimal digit of the CSA29. A decimal addition is carried out for the first intermediate product and the product of a decimal part after the bit positioning is carried out to the sum obtained after a carry correction.

29. 发明专利

JPS58129654A MULTIPLICATION SYSTEM 失效
公开(公告)号：JPS58129654A
公开(公告)日：1983-08-02
申请号：JP1162782
申请日：1982-01-29
申请人： HITACHI LTD
发明人： FUKUDA MASAHARU , OOSHIMA YOSHIO , ISHIKAWA SUKETAKA , OOTSUKI TOORU
IPC分类号： G06F7/53 , G06F7/508 , G06F7/52 , G06F7/527
摘要： PURPOSE:To execute multiplication with a multiplying time proportional to a smaller value between the 1st operand length - 2nd operand length and the 2nd operand length, by determining a multiplier and a multiplicand from the compared result between the 1st operand length - the 2nd operand length and the 2nd operand length. CONSTITUTION:It is defined that the variable length of an operand (OP) 1 specified by the 1st address is L1 and the variable length of an operand (OP) 2 specified by the 2nd address is L2. If L1-L2 =L2, the OP1 and the OP2 are set up in the multiplicand register 16 and the multiplier register 17 respectively.

30. 发明专利

JPS5786953A OPERAND ADDRESS DISCRIMINATOR 失效
公开(公告)号：JPS5786953A
公开(公告)日：1982-05-31
申请号：JP16358280
申请日：1980-11-20
申请人： HITACHI LTD
发明人： NISHISAKA MINORU , ISHIKAWA SUKETAKA
IPC分类号： G06F7/00 , G06F7/76 , G06F9/308 , G06F9/34 , G06F12/02
摘要： PURPOSE:To speed discrimination timing by decreasing the number of operators by discriminating a difference value between both operand addresses found by the operators and by comparing it with the result of the descrimination of operand-length discriminating circuits. CONSTITUTION:An operator 3 finds a difference value between the operand addresses OA1 and OA2 of the 1st and 2nd registers 1 and 2, and difference discriminating circuits 4 and 5 discriminate a

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