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1. 发明专利

JP2001045041A NETWORK CONFIGURATION METHOD AND PATH DECIDING METHOD 失效
公开(公告)号：JP2001045041A
公开(公告)日：2001-02-16
申请号：JP22084599
申请日：1999-08-04
申请人： HITACHI LTD
发明人： MAEJIMA YASUHITO , YABE HIDEAKI
IPC分类号： G06F15/16 , H04L12/28 , H04L12/46 , H04L12/701 , H04L12/715 , H04L12/56
摘要： PROBLEM TO BE SOLVED: To allow the Internet or the like where a plurality of autonomous systems are interconnected to attain high speed routing. SOLUTION: Autonomous system groups 10, 20, 30, 40, 50 being components of the Internet or the like are grouped, and border routers 11, 12, 21, 31 of a group 1 and border routers 41, 51 of a group 2 share path information respectively. Each border router is provided with a means that separates a desired autonomous system of the group of integrates an autonomous system of other groups in response to traffic and stores path information in matching with a processing capability of the border routers in the group.

2. 发明专利

JPH0413735B2 失效
公开(公告)号：JPH0413735B2
公开(公告)日：1992-03-10
申请号：JP19661882
申请日：1982-11-09
申请人： HITACHI LTD
发明人： YABE HIDEAKI , OOSHIMA YOSHIO , ISHIKAWA SUKETAKA , OOTSUKI TOORU , FUKUDA MASAHARU
IPC分类号： G06F7/491 , G06F7/493 , G06F7/496 , G06F7/52

3. 发明专利

JPS5987543A BINARY CODED DECIMAL NUMBER DIVIDING SYSTEM 失效
公开(公告)号：JPS5987543A
公开(公告)日：1984-05-21
申请号：JP19661882
申请日：1982-11-09
申请人： HITACHI LTD
发明人： YABE HIDEAKI , OOSHIMA YOSHIO , ISHIKAWA SUKETAKA , OOTSUKI TOORU , FUKUDA MASAHARU
IPC分类号： G06F7/491 , G06F7/493 , G06F7/496 , G06F7/52
摘要： PURPOSE:To select directly a desired multiple value register, to reduce the number of gate stages, and to execute the processing at a high speed by modifying in advance a data to be stored in a quotient forecasting table. CONSTITUTION:A value modified to (0110)2-(1111)2 containing a redundant part of a binary coded decimal representation is stored in a quotient forecasting table 4 of a binary coded decimal number dividing system. Also, each upper bit of a dividend register 1 and a divisor register 3 is set as an address of the table, and a value read out of the table 4 is set as a value which modifies +6 to the forecasting quotient. The lower three bits of four bits of the forecasting quotient read out of this table 4 are used directly as a selecting signal of a multiple value register 7, and a multiple is selected. Also, at the same time, 6 is subtracted by a -6 circuit 10 of a quotient determining circuit 11, and thereafter, it is stored in a forecasting quotient register 5. Subsequently, a multiple value of a divisor from the register 7 is added to a decimal adder and subtracter 8, is subtracted from a dividend value of the register 1, a value derived by the circuit 11 is stored in a register 2, and the processing can be executed at a high speed.

4. 发明专利

JPH0234054B2 失效
公开(公告)号：JPH0234054B2
公开(公告)日：1990-08-01
申请号：JP11955683
申请日：1983-07-01
申请人： HITACHI LTD
发明人： OOTSUKI TOORU , OOSHIMA YOSHIO , ISHIKAWA SUKETAKA , YABE HIDEAKI , FUKUDA MASAHARU
IPC分类号： G06F7/496 , G06F7/491 , G06F7/506 , G06F7/508 , G06F7/52 , G06F7/527

5. 发明专利

JPS5794972A INFORMATION PROCESSOR 失效
公开(公告)号：JPS5794972A
公开(公告)日：1982-06-12
申请号：JP16960880
申请日：1980-12-03
申请人： HITACHI LTD
发明人： YABE HIDEAKI , ISHIKAWA SUKETAKA
IPC分类号： G06F12/16 , G06F11/00 , G06F12/08
摘要： PURPOSE:To continue processing without using a buffer storage BS even if the contents of an address register has an error, by sending a coincidence signal only when the contents of the address buffer and those of a buffer address array BAA are coincident with each other. CONSTITUTION:When an error detector 14 detects an error, a comparator 15 supplies a dissidence signal to an AND gate 17 through a line 15b without reference to coincidence between the high-order address bits of an address register 11 and a BAA 12. Then, data from a BS13 is not used and the address of the register 11 is supplied to an MS to output the readout data of the MS through the gate 17 and an OR gate 18. The dissidence signal opens AND gates 19 and 20 to store new data from the MS and its corresponding address in the BS13 and BAA12. Thus, processing is continued by using the data in the MS without using the BS13.

6. 发明专利

JPS6011927A DECIMAL MULTIPLYING DEVICE 失效
公开(公告)号：JPS6011927A
公开(公告)日：1985-01-22
申请号：JP11955683
申请日：1983-07-01
申请人： HITACHI LTD
发明人： OOTSUKI TOORU , OOSHIMA YOSHIO , ISHIKAWA SUKETAKA , YABE HIDEAKI , FUKUDA MASAHARU
IPC分类号： G06F7/496 , G06F7/491 , G06F7/506 , G06F7/508 , G06F7/52 , G06F7/527
摘要： PURPOSE:To obtain a multiplying device which can perform a decimal loop addition at a high speed by using the double input of a 3-input carry save adder as the input of an intermediate product which is shown in the form of a carry and another input as the input of the product of a decimal part. CONSTITUTION:The double input of a 3-input carry save adder is used as the input of an intermediate product shown in the form of a carry, and another input is used as the input of the product of a decimal part. For instance, 6 is added every decimal digit by a 6-addition correcting circuit 28 as the initial setting to start the loop addition. Then the intermediate product held in the form of a sum and a carry is added with the product to a decimal part obtained by another arithmetic means by a 3-input carry save adder CSA29. Then the correction is given to the sum output as well as to an upper decimal digit from a sum output correction circuit 31 and a decimal upper digit corretion circuit 32 for each decimal digit of the CSA29. A decimal addition is carried out for the first intermediate product and the product of a decimal part after the bit positioning is carried out to the sum obtained after a carry correction.

7. 发明专利

JPS59173843A Dividing device 失效
标题翻译：分体装置
公开(公告)号：JPS59173843A
公开(公告)日：1984-10-02
申请号：JP4714783
申请日：1983-03-23
申请人： Hitachi Ltd
发明人： FUKUDA MASAHARU , OOSHIMA YOSHIO , ISHIKAWA SUKETAKA , OOTSUKI TOORU , YABE HIDEAKI
IPC分类号： G06F7/493 , G06F7/496 , G06F7/508 , G06F7/52 , G06F7/535
CPC分类号： G06F7/535
摘要： PURPOSE:To read out an estimated quotient at a high speed by using an RAM having small storage capacity by dividing a quotient estimating table into plural parts and selecting one output out of plural ones from the quotient estimating table by bit strings of the divisor and divident. CONSTITUTION:A bit string consisting of respective upper bits of a divident register 1 and a divisor register 3 is inputted to a logical circuit 40 as a bit string 41. A bit string excluding the lower 2-bit of the bit string 41 is inputted to four quotient estimating tables 4200, 4201, 4210, 4211 as a common address through a line 41a. The 2nd bit from the lowmost bit of the bit string 41 is inputted to comparators 4300, 4301, 4310, 4311 through a line 41b and the lowmost bit is inputted to AND gates 4400, 4401, 4410, 4411. All outputs of the AND gates 4400, 4401, 4410, 4411 are inputted to an OR gate 45 and the output of the OR gate 45 is inputted to an estimated quotient register 5.
摘要翻译：目的：通过将商估计表分成多个部分，通过使用具有小存储容量的RAM来高速读出估计商，并通过除数和除数的位串从商估计表中选择一个输出。构成：将由除数寄存器1的各高位组成的位串和除数寄存器3作为比特串41输入到逻辑电路40.将比特串41的下位2除外的比特串输入到四个商估计表4200,4201,41210,41211作为通过线41a的公共地址。来自比特串41的最低位的第二比特通过线路41b输入到比较器4300,4123,4310,41311，并且最低位被输入到与门4400,4401,4107,411。AND门的所有输出 4400,4401,4410,4411被输入到或门45，或门44的输出被输入到估计商寄存器5。

8. 发明专利

JPH0729005A PERSONAL IDENTIFICATION SYSTEM 失效
公开(公告)号：JPH0729005A
公开(公告)日：1995-01-31
申请号：JP15483293
申请日：1993-06-25
申请人： HITACHI LTD
发明人： YABE HIDEAKI , WATANABE YASUSHI
IPC分类号： G06T7/00 , G06F19/00 , G06Q10/00 , G06Q20/40 , G06Q40/00 , G06Q40/02 , G06Q50/00
摘要： PURPOSE:To provide a personal identification system which prevents the illegal use of a personal resource and whose security is higher in a computer system. CONSTITUTION:At the time of using the system, a user reads an ID card by a pen input system 5, sets an input condition such as the color and thickness of a pen and inputs a sign and a mark by an input pen. The inputted sign (mark) is recognized by a pattern recognition means 6, a write order recognition means 7 and an input condition recognition means 8 as respective data, and an ID number and sign (mark) information are transferred to a host system 9. The host system 9 searches sign (mark) information which is previously registered in a user data base 14 with card ID as a key, data-collates sign (mark) information having same ID, a pattern, a write order and the input condition by a pattern collation processing part 10, a write order collation processing part 11 and an input condition collation processing part 12. Only when they coincide, the use of the system is permitted.

9. 发明专利

JPH0578049B2 失效
公开(公告)号：JPH0578049B2
公开(公告)日：1993-10-28
申请号：JP2753183
申请日：1983-02-23
申请人： HITACHI LTD
发明人： OOTSUKI TOORU , OOSHIMA YOSHIO , ISHIKAWA SUKETAKA , YABE HIDEAKI , FUKUDA MASAHARU
IPC分类号： G06F7/487 , G06F5/01 , G06F7/507 , G06F7/508 , G06F7/527 , G06F7/52 , G06F7/00

10. 发明专利

JPS59184944A Rounding arithmetic system 失效
标题翻译：圆形算术系统
公开(公告)号：JPS59184944A
公开(公告)日：1984-10-20
申请号：JP5924083
申请日：1983-04-06
申请人： Hitachi Ltd
发明人： ISHIKAWA SUKETAKA , OOSHIMA YOSHIO , YABE HIDEAKI , FUKUDA MASAHARU , OOTSUKI TOORU
IPC分类号： G06F7/38 , G06F7/48 , G06F7/483
CPC分类号： G06F7/48 , G06F7/49963
摘要： PURPOSE:To facilitate an easy rounding arithmetic system by adding a data pattern where only the position corresponding to the operand data and its prescribed bit is set at (1) with other positions set at (0). CONSTITUTION:The operand data consists of (m) bits and requires up to (n) bits (m>n) as a result of a rounding operation. In such a case, only (n+1) bits are set at (1) with other bits set at (0) in a data pattern. Such a pattern is added with the operand data. Then the carry-up is produced when the (n+1) bits of the operand data are set at (1). Then the generation of the carry-up is inhibited when said (n+1) bits are set at (0). Thus the rounding operation is facilitated for the operand data of (n+1) bits.
摘要翻译：目的：为了方便一个简单的舍入算术系统，通过添加一个数据模式，其中只有与操作数数据相对应的位置及其规定的位被设置为（1），其他位置设置为（0）。构成：操作数数据由（m）位组成，由于舍入操作需要最多（n）位（m> n）。在这种情况下，在数据模式中，只有（n + 1）位被设置为（1），其他位设置为（0）。这样一个模式加上操作数数据。然后，当操作数数据的（n + 1）位被设置为（1）时产生进位。那么当所述（n + 1）位被设置为（0）时，禁止产生加载。因此，对于（n + 1）位的操作数数据，舍入操作变得容易。

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