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1. 发明专利

JPH0351924A PROCESSOR SCAN CONTROL SYSTEM 失效
公开(公告)号：JPH0351924A
公开(公告)日：1991-03-06
申请号：JP18716889
申请日：1989-07-19
申请人： HITACHI LTD
发明人： FUKUDA KIMIO , ISHIYAMA AKIRA
IPC分类号： G06F15/16 , G06F11/22 , G06F15/177
摘要： PURPOSE:To suppress the increase of exclusive interfaces to a maintenance processor by performing a scan operation based on a scan instruction given from a processor connected to the maintenance processor via a common bus. CONSTITUTION:When a scan instruction of a processor 5, for example, is given to a processor 3 from a maintenance processor 1 via a maintenance processor interface 101, a maintenance processor interface control part 37 transmits a scan control signal 374 via a start control selection circuit 38 and an end control output selection circuit 39. In other words, a scan signal to be applied to the processor 5 is sent to a start control bus 800 and the address of a register stored in the processor 5 and to be scanned is sent to an end control bus 900 respectively. Thus it is just required to connect the interface secured to the processor 1 to a single processor. Then no interface is required to other processors for the scan control.

2. 发明专利

JPS62282344A BUFFER MANAGEMENT CIRCUIT 失效
公开(公告)号：JPS62282344A
公开(公告)日：1987-12-08
申请号：JP12591087
申请日：1987-05-25
申请人： HITACHI LTD
发明人： FUKUDA KIMIO , MAKIURA YASUHIKO
IPC分类号： G06F12/02 , G06F12/08 , G06F12/16
摘要： PURPOSE:To suppress the duplex releasing of a buffer by using a buffer management unit to discriminate whether or not a buffer released from a processor is a buffer released duplicatedly. CONSTITUTION:When a buffer address is released from a processor, an address generating circuit 16 generates the address of a buffer address memory 1 storing a buffer address assigning a buffer loop. A buffer address on a buffer data line 6 read by the address and an opened buffer address on a buffer data line 7 are compared by a comparator 15. The operation above is applied to all the buffer pools and in case of the coincidence as the result of comparison, it is transferred to the process via a control line 17 to which the address is disabled for releasing and a series of operation for buffer releasing is not executed in the buffer management unit.

3. 发明专利

JPS62214418A TIME CORRECTING SYSTEM FOR TIMEPIECE INCORPORATED IN PROCESSOR 失效
公开(公告)号：JPS62214418A
公开(公告)日：1987-09-21
申请号：JP5681486
申请日：1986-03-17
申请人： HITACHI LTD
发明人： GENMA HIDEAKI , FUKUDA KIMIO
IPC分类号： G04C9/04 , G04G5/00 , G06F1/00 , G06F1/14
摘要： PURPOSE:To correct a timepiece incorporated in a processor with a high accuracy by providing a means which compares a time counter in a service processor with that in a processor and stopping write and counting-up of the counter in accordance with the comparison result. CONSTITUTION:A processor 1 consists of an instruction processor 3, a time counter 4, an oscillating circuit 5, etc., and a service processor 2 consists of a time counter 12, an oscillating circuit 14, a control circuit 15, a timer 16, a comparing circuit 17, a counter 18, an FF 20, etc. The control circuit 15 sets an initial count value to the timer 16 at the initial program loading time; and when this count value becomes zero, the circuit 15 issues an interrupt signal 25 to compare values of time counters 4 and 12 with each other in the comparing circuit 17. If they are coincide with each other as the comparison result, the initial count value is set again. If the value of the counter 4 is smaller, the value of the counter 12 is set to the counter 4; but if the value of the counter 4 is larger, the difference is set to the counter 18 and counting-up of the counter 4 is stopped and restarted to correct the time.

4. 发明专利

JPS6225355A METHOD FOR PROPAGATING SIGNAL BETWEEN INTEGRATED CIRCUITS 失效
公开(公告)号：JPS6225355A
公开(公告)日：1987-02-03
申请号：JP16410685
申请日：1985-07-26
申请人： HITACHI LTD
发明人： HIRAMATSU MASATAKA , FUKUDA KIMIO
IPC分类号： G06F13/12
摘要： PURPOSE:To decrease the number of input/output signal lines of an integrated circuit by managing with (n) input/output signal lines in total for (n) integrated circuits. CONSTITUTION:A resistance 12 is given such a resistance value that a signal line 23 is held at a high level by the resistance 12 when output levels of output gates 10 and 11 of integrated circuits 1 and 2 are both high impedance and held at a low level when even either one is at a low level. Consequently, the output levels of the output gates 10 and 11 are ORed on the signal line 23 and the result is the input level of input gates 7 and 8 of the integrated circuits 1 and 2. Therefore, two input/output signal lines are enough for the two integrated circuits and the number of input/output signal lines of the integrated circuits is reducible.

5. 发明专利

JPH07295697A HOT PLUG INSERTION AND EXTRACTION DEVICE 失效
公开(公告)号：JPH07295697A
公开(公告)日：1995-11-10
申请号：JP8287094
申请日：1994-04-21
申请人： HITACHI LTD
发明人： FUKUDA KIMIO , MORITA KAZUO
IPC分类号： G06F3/00 , H02H9/00
摘要： PURPOSE:To exert no influence upon the power sources of other loads and prevent other loads from malfunctioning by supplying a rush current, bit by bit, by a circuit which supplies the rush current and opening a power supply path after the supply of the rush current is completed. CONSTITUTION:In addition to a connector 32, a power source and a control circuit such as a processor which controls the respective loads 2 are mounted on a printed circuit board 33. Then the reception pins of the connector 11 on the side of a hot plug insertion and extraction unit l are all equal in length and connected to a load 2 from the connector 11 through cables 12a and 12b and further connectors 24 and 25. Power receiving circuits 21a and 21 do not open an original power feed path in normal operation at the time of insertion, and the rush current is supplied, bit by bit, by another circuit; after the supply of the rush current is nearly completed, the original electric feed path is opened to supply electricity to the whole load 2. Thus, the rush current to the power terminal of the load as an object of hot plug insertion and extraction is suppressed and the original electric feeding circuit is opened thereafter, so no influence on the power sources of other loads is exerted to prevent other loads from malfunctioning.

6. 发明专利

JPH04251368A BUS CONTROL SYSTEM 失效
公开(公告)号：JPH04251368A
公开(公告)日：1992-09-07
申请号：JP1147591
申请日：1991-01-08
申请人： HITACHI LTD , HITACHI INFORMATION NETWORK
发明人： NAKAJIMA MASAMICHI , FUKUDA KIMIO
IPC分类号： G06F13/38 , G06F13/42 , G06F15/16 , G06F15/177
摘要： PURPOSE:To perform high-performance data transfer and command transfer suitable for the response speed of each processor without deteriorating the responsiveness of the processors which can make high-speed responses. CONSTITUTION:Plural processors 8-11 are divided into two groups, namely, one group of processors 8 and 9 which can make high-speed responses and the other group of processors 10 and 11 which cannot make high-speed responses and control buses 5A and 5B are provided in corresponding to the two groups. The processors 8 and 9 and processors 10 and 11 respectively transfer data or commands through the control bus 5A and a common unit command bus 6 and through the control bus 5B and the command bus 6 in accordance with their responding speeds.

7. 发明专利

JPH02118710A METHOD AND CIRCUIT FOR DETECTING STEP-OUT 失效
公开(公告)号：JPH02118710A
公开(公告)日：1990-05-07
申请号：JP27175988
申请日：1988-10-27
申请人： HITACHI LTD
发明人： FUKUDA KIMIO
IPC分类号： G06F1/14 , G06F1/04 , G06F15/16
摘要： PURPOSE:To attain the easy time step-out detection of control by providing parity data generation circuits with the contents of all the counters and exclusive OR circuits inputting the outputs of the parity data generation circuits. CONSTITUTION:The parity data generation circuits 13 and 23 with all the bits of the time counters 11 and 21 are provided, and parity data of one bit in the circuits are outputted to signal lines 4 and 5. Then, the exclusive OR circuits 14 and 24 for comparing the outputs of the parity data generation circuits 13 and 23 on the signal lines 4 and 5 are provided. When the outputs of the parity data generation circuits 13 and 23 in respective processors differ, the outputs of the exclusive OR circuits 14 and 24 come to '1', and time-step out is detected. Thus, step-out between the processors can be detected by simple constitution by comparing the contents of all the counters in multi-processor systems 1 and 2 where plural clock counters 11 and 12 exist.

8. 发明专利

JPH01290313A SIGNAL PROPAGATING METHOD BETWEEN INTEGRATED CIRCUITS 失效
公开(公告)号：JPH01290313A
公开(公告)日：1989-11-22
申请号：JP12022388
申请日：1988-05-17
申请人： HITACHI LTD
发明人： FUKUDA KIMIO , FUKUNAKA HIDETADA , UCHIDA SATORU
IPC分类号： H03K19/0175 , H03K19/00 , H04L25/02
摘要： PURPOSE:To decrease the delay time of an output of a wired OR and to send a high speed signal by bringing the level of an output gate to either a high level or a low level to be made stable by a resistor and then bringing the state into a high impedance state. CONSTITUTION:When the level of a control signal generating circuit 3 changes from a high level to a low level, an inverter 5 goes to a high level and an AND gate 7 goes to a high level. Since a flip-flop 4 outputs a high level at a point of time, an OR gate 6 remains at a high level. Then the output gate 8 goes from a low level to a high level. Thus, the flip-flop goes to a low level by using a clock signal and the OR gate 6 goes to a low level, the output gate 8 goes to a high impedance state.

9. 发明专利

JPS63201810A TIME SYSTEM FOR INFORMATION PROCESSING SYSTEM 失效
公开(公告)号：JPS63201810A
公开(公告)日：1988-08-19
申请号：JP3535687
申请日：1987-02-18
申请人： HITACHI LTD
发明人： FUKUDA KIMIO
IPC分类号： G06F1/14 , G06F1/00 , G06F15/16
摘要： PURPOSE:To make a system efficient and high-performance by providing one time circuit in a main storage control controller and sharing this time circuit among processor. CONSTITUTION:In case of read/write from a processor 4 or 5 to a shared time circuit 3, this processor issues an access request to a main storage controller 2 in the same manner as read/write to a main storage device 1, and read/write to the main storage device 1 or that to the time circuit 3 is indicated by the access classification. The main storage controller 2 accesses the main storage device 1 or the time circuit 3 in accordance with the access classification and sends the result to the processor 4 or 5.

10. 发明专利

JPH03179534A FAULTY PROCESSOR DISCRIMINATING SYSTEM 失效
公开(公告)号：JPH03179534A
公开(公告)日：1991-08-05
申请号：JP31963489
申请日：1989-12-08
申请人： HITACHI LTD
发明人： FUKUDA KIMIO
IPC分类号： G06F15/16 , G06F11/22 , G06F15/177
摘要： PURPOSE:To suppress the increase of the number of signal lines and to recognize a processor having a fault by transmitting the identification information on the faulty processor to the processors except the faulty one when a processor discriminates the faulty processor. CONSTITUTION:When the fault is detected by the fault detecting part 11 of a processor 1, a fault occurrence reporting signal 10 is transmitted and an OR output 101 is applied to the processors 2 - n respectively via an OR gate 100. Thus these processors know that either one of processors has a fault in a system. When the signal 101 is received, the bus securing requiring signals 24 - n4 are sent to a bus arbiter 200 from the common bus control parts 22 - n2 of the processor 2 - n. The arbiter 200 selects the processor 2 and sends a bus using permitting signal 25 to the processor 2. The processor 2 discriminates the processor having the fault via a bus 300 and reports this faulty processor to other processors.

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