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11. 发明专利

JPS61193456A MANUFACTURE OF SEMICONDUCTOR ELEMENT 失效
公开(公告)号：JPS61193456A
公开(公告)日：1986-08-27
申请号：JP3318385
申请日：1985-02-21
申请人： TOSHIBA CORP , TOSHIBA CERAMICS CO
发明人： YAMABE KIKUO , TAKAI NORIHEI , SHIRAI HIROSHI , WATANABE MASAHARU
IPC分类号： H01L21/26 , H01L21/316 , H01L21/322 , H01L21/324
摘要： PURPOSE:To suppress the generation of lattice defects related to conductivity in a process of the formation of a thermal oxide film by a method wherein hydrogen is caused to join unsaturated bonds in a silicon wafer surface when the silicon wafer is subjected to heat treatment in a hydrogen atmosphere. CONSTITUTION:A thermal oxide film 12 is formed on the surface of a silicon wafer 11, a resist 13 is applied to the entire surface, and then etching is accom plished for the removal of the thermal oxide film 12 from a region planned for the formation of a gate oxide film. The silicon wafer 11 is then subjected to an RCA rinse and washing with water for the formation of a thin natural oxide film 14. Next, the wafer 11 is irradiated with light from a lamp, a halogen lamp for example, for the rise of the wafer surface temperature up to 1,000[ deg.C], and is left for a minute in argon gas including some hydrogen. In this process, unsaturated bonds present in the surface of the silicon wafer 11 accept hydrogen atoms for saturation. Next, a thermal oxide film 15 is formed on the wafer surface,which is followed by the formation of a polycrystalline silicon film 16.

12. 发明专利

JPS61176125A DEFECT REDUCING METHOD FOR THIN SILICON THERMALLY OXIDED FILM 失效
公开(公告)号：JPS61176125A
公开(公告)日：1986-08-07
申请号：JP1528185
申请日：1985-01-31
申请人： TOSHIBA CORP
发明人： YAMABE KIKUO
IPC分类号： H01L21/316
摘要： PURPOSE:To suppress the generation of defects in electric conduction of a thermally oxided film as well as to obtain a homogenous thermally oxided film by a method wherein, after a natural oxide film is removed from a silicon wafer in a high temperature and high vacuum atmosphere, a contaminant is prevented from adhering to the silicon after by controlling the atoms to be connected to the unsaturated coupling of surface silicon atoms. CONSTITUTION:A hydrogen combustion oxidation is performed on an Si wafer 1, and a thermal oxide film 2 is formed. Subsequently, after a resist 3 is coated, the oxide film 2 of a thin gate oxide film formed region 4 is removed by etching by performing a photoetching method. Then, a natural oxide film 5 is formed by performing an RCA treatment and a rinsing. The silicon wafer 1 is then heated up to 700 deg.C or above in the high vacuum atmosphere of 10 torr or below, and the natural oxide film 5 is removed. Subsequently, the above is exposed to the argon gas atmosphere containing hydrogen gas, and hydrogen atoms are coupled to the unsaturated coupling on the silicon surface. Then, a gate oxide film 6 is formed by the oxidation performed in an argon gas atmosphere, and subsequently a polycrystalline silicon film 7 of approximately 0.4mum is formed by performing an LPCVD method. Moreover, a gate electrode pattern 8 is formed by performing a photoetching method after the resistance of the polycrystalline silicon film 7 is lowered using a POCl3 diffusing method.

13. 发明专利

JPS5922342A Manufacture of semiconductor device 失效
标题翻译：半导体器件的制造
公开(公告)号：JPS5922342A
公开(公告)日：1984-02-04
申请号：JP13242382
申请日：1982-07-29
申请人： Toshiba Corp
发明人： YAMABE KIKUO
IPC分类号： H01L21/76 , H01L21/316 , H01L21/762
CPC分类号： H01L21/76216
摘要： PURPOSE:To make the insulating film of gate oxide film, etc., to be formed on the surface of a substrate to have no defect when field oxide films are to be formed according to the selective oxidation method by a method wherein a polycrystalline silicon film is put between silicon nitride films to be used as the non- oxidizable film. CONSTITUTION:A silicon oxide film 2 is formed on the P type silicon substrate 1, and the first silicon nitride film 4 of the degree of 1,000Angstrom thickness, the polycrystalline silicon film 5 of 1,000Angstrom thickness and the second silicon nitride film 6 of 500Angstrom thickness are deposited in order to constitute the non-oxidizable film 3 according to the CVD method, for example. Then boron ion implanted layers 8 are formed in the substrate 1 of the field regions. After a resist film 7 is removed in succession, oxidation is performed in the wet oxygen atmosphere at 1,000 deg.C using the non-oxidizable film 3 as the mask to make the field oxide films 9 of 1.0mum thickness to grow. At this time, an oxidizing agent, namely steam and oxygen, or ammonia and nitrogen generated by reaction of the oxidizing agent and the silicon nitride film 4 are made to react with polycrystalline silicon 5 to prevent the substrate 1 from formation of a nitride on the surface.
摘要翻译：目的：为了使形成在基板表面上的栅极氧化膜等的绝缘膜根据选择性氧化法形成场氧化膜，不会发生缺陷，其中多晶硅膜放置在用作不可氧化膜的氮化硅膜之间。构成：在P型硅基板1上形成氧化硅膜2，厚度为1000的第一氮化硅膜4，1000A厚度的多晶硅膜5以及500Ang的第二氮化硅膜6 沉积厚度以便例如根据CVD方法构成不可氧化膜3。然后在场区的衬底1中形成硼离子注入层8。在连续除去抗蚀剂膜7之后，使用不可氧化膜3作为掩模在1000℃的湿氧气氛中进行氧化，使得1.0μm厚的场氧化膜9生长。此时，通过氧化剂和氮化硅膜4的反应产生的氧化剂，即蒸汽和氧气，或氨和氮使其与多晶硅5反应，以防止衬底1上形成氮化物表面。

14. 发明专利

JP2006196908A Semiconductor device manufacturing method, manufacturing equipment, simulation method, and simulator 有权
标题翻译：半导体器件制造方法，制造设备，仿真方法和仿真器
公开(公告)号：JP2006196908A
公开(公告)日：2006-07-27
申请号：JP2006007760
申请日：2006-01-16
申请人： Toshiba Corp , 株式会社東芝
发明人： ONGA SHINJI , OKADA TAKAKO , TOMITA HIROSHI , YAMABE KIKUO , OKANO HARUO
IPC分类号： H01L21/00 , G06F17/50 , G06F19/00 , H01L21/02 , H01L21/316 , H01L21/336 , H01L21/76 , H01L21/8246 , H01L27/105 , H01L29/78
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device manufacturing method which can proceed a semiconductor device manufacturing process, without a test piece, as desired process or while correcting the process. SOLUTION: The semiconductor device manufacturing method, made up of a plurality of processes, includes a process to obtain a real observation data in at least one of the plurality of processes, a process of obtaining a forecasting data in at least one in of the plurality of processes by an abinitio molecular dynamics process simulator or a molecular dynamics simulator provided with an experimental potential, a process of relatively checking the forecast data and actual observed data in real time successively, and a process of correcting the manufacturing process factors in real time successively, when a significant difference has been recognized between the set value of the manufacturing process factor and the plurality of manufacturing process factors predicted from the real observed data. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供一种半导体器件制造方法，其可以根据期望的工艺进行半导体器件制造工艺，而不需要测试片，或者在校正工艺时。解决方案：由多个处理组成的半导体器件制造方法包括在多个处理中的至少一个中获得真实观测数据的处理，获得至少一个处理中的预测数据的处理的分子动力学过程模拟器或具有实验潜力的分子动力学模拟器的多个过程，连续相对地检查预测数据和实际观测数据的过程，以及校正制造工艺因素的过程当在制造工艺因素的设定值和从实际观察数据预测的多个制造工艺因素之间已经识别出显着差异时，依次实时地进行。版权所有（C）2006，JPO＆NCIPI

15. 发明专利

JP2006013525A Manufacturing method of semiconductor apparatus, manufacturing apparatus, simulation method and simulator 审中-公开
标题翻译：半导体装置的制造方法，制造装置，模拟方法和模拟器
公开(公告)号：JP2006013525A
公开(公告)日：2006-01-12
申请号：JP2005200821
申请日：2005-07-08
申请人： Toshiba Corp , 株式会社東芝
发明人： ONGA SHINJI , OKADA TAKAKO , TOMITA HIROSHI , YAMABE KIKUO , OKANO HARUO
IPC分类号： H01L29/78 , H01L21/00 , H01L21/02 , H01L21/336
摘要： PROBLEM TO BE SOLVED: To provide a manufacturing method of a semiconductor apparatus which enables a semiconductor apparatus manufacturing process to be proceeded without a test piece as a desired process or while amendments being effected. SOLUTION: In a manufacturing method of a semiconductor apparatus comprising a plurality of processes, actual observation data in at least one of the plurality of processes is obtained. Prediction data in at least one of the plurality of processes is obtained by an abinitio molecular dynamics process simulator or a molecular dynamics simulator provided with empirical potential. Then, the prediction data and the actual observation data are compared and tested successively in an actual time. When a significant difference is recognized between a set value of a manufacturing process factor and a factor of the plurality of manufacturing processes gathered from the actual observation data according to the comparison and test, the manufacturing process factor is amended successively in an actual time. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供一种半导体装置的制造方法，其能够使半导体装置制造工艺在没有试件作为期望的工艺的情况下进行，或者在实施修改的同时进行。解决方案：在包括多个处理的半导体装置的制造方法中，获得多个处理中的至少一个中的实际观测数据。在多个过程中的至少一个过程中的预测数据通过具有经验潜力的分析动力学过程模拟器或分子动力学模拟器获得。然后，在实际时间中连续地比较和测试预测数据和实际观察数据。当根据比较和测试从制造过程因子的设定值和从实际观察数据收集的多个制造过程的因子之间识别出显着差异时，制造过程因素在实际时间中连续地被修改。版权所有（C）2006，JPO＆NCIPI

16. 发明专利

JPH07263453A SEMICONDUCTOR DEVICE AND ITS MANUFACTURE 失效
公开(公告)号：JPH07263453A
公开(公告)日：1995-10-13
申请号：JP5429994
申请日：1994-03-25
申请人： TOSHIBA CORP
发明人： TOMITA HIROSHI , YAMABE KIKUO , SAITO MASAMI
IPC分类号： H01L21/322 , H01L29/32
摘要： PURPOSE:To improve thermal stability as compared with the conventional IG, BPS gettering, and increase the capacitance of a gettering site, in a low temperature process at 500 deg.C or lower after a metal wiring formation process in which a high temperature heat process can not be used, by forming an amorphous semiconductor film on the rear of a semiconductor substrate. CONSTITUTION:The title device is consists of a semiconductor substrate 101, an element which is formed on the surface side of the substrate 101 and has electrode wirings 111, 115 composed of metal, and an amorphous semiconductor film 102 formed on the back side of the substrate 101. For example, an amorphous silicon film 102 to which boron (10 atom/cm is added is formed on the rear of the silicon substrate 101 on which elements such as a transistor and a capacitor are formed. The amorphous silicon film 102 to which boron is added can be formed by, e.g. a low pressure chemical vapor deposition method using diborane and disilane, at a low temperature of about 300 deg.C, so that the film 102 can be formed without any troubles after metal wirings are formed.

17. 发明专利

JPH06268234A SEMICONDUCTOR DEVICE AND MANUFACTURE THEREOF 失效
公开(公告)号：JPH06268234A
公开(公告)日：1994-09-22
申请号：JP8011793
申请日：1993-03-15
申请人： TOSHIBA CORP
发明人： MINAZU YASUMASA , HAZAMA HIROAKI , OZAWA YOSHIO , YAMABE KIKUO , MOMOSE HISAYO , ONO TAMASHIRO , AKASAKA YASUSHI
IPC分类号： H01L21/318 , H01L21/8247 , H01L29/78 , H01L29/788 , H01L29/792
摘要： PURPOSE:To provide a semiconductor device wherein a problem caused by an asymmetrical distribution of nitrogen concentration in an insulating film of oxynitride film is solved. CONSTITUTION:A field effect transistor is formed on a silicon substrate 1 for a memory cell of an EEPROM, and a tunnel gate insulating film is composed of a thermal oxide film 3, an oxynitride film 4, and a thermal oxide film 5, wherein the concentration of nitrogen contained in tire tunnel gate insulating film is maximal at its center and symmetrical to its thicknesswise direction.

18. 发明专利

JPH0590254A MANUFACTURE OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH0590254A
公开(公告)日：1993-04-09
申请号：JP24981091
申请日：1991-09-27
申请人： TOSHIBA CORP
发明人： TSUNASHIMA YOSHITAKA , KIYOTOSHI MASAHIRO , YAMABE KIKUO
IPC分类号： H01L21/265 , H01L21/316 , H01L21/318 , H01L21/324
摘要： PURPOSE:To provide a method of manufacturing a semiconductor device, where thermal oxide films different in thickness can be formed on a semiconductor substrate or a semiconductor film without increasing manufacturing processes in number. CONSTITUTION:A first process where a nitriding preventive film 9 is formed on a silicon substrate 1 in a cell region A, a second process where the surface of a silicon substrate in a peripheral circuit region B is nitrided in an atmosphere of ammonia, a third process where the nitriding preventive film 9 is removed, and a fourth process where thermal oxide films 12a and 12 are formed on the silicon substrate in both the cell region A and the peripheral circuit region B are provided.

19. 发明专利

JPH0590117A SINGLE CRYSTAL THIN FILM SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH0590117A
公开(公告)日：1993-04-09
申请号：JP24817091
申请日：1991-09-27
申请人： TOSHIBA CORP
发明人： KANBAYASHI SHIGERU , ONGA SHINJI , YAMABE KIKUO
IPC分类号： H01L21/02 , H01L21/336 , H01L27/00 , H01L27/12 , H01L29/04 , H01L29/78 , H01L29/786
摘要： PURPOSE:To enable using crystal orientation and crystal axis suitable to an element to be formed on each layer, and using a substrate advantageous to chip working, by adhering two or more wafers having different crystal orientations, and forming elements on these wafers. CONSTITUTION:An N-channel MOS is formed on a silicon wafer having a (100) face, and element isolation and activation are performed. At the same time, a P-channel MOS is formed on a silicon wafer having a (110) face. Each of the oxidation periods is adjusted so as to be matched with each of the crystal faces. The respective wafers are dipped in pure water, stuck to each other in the water, taken out from the water, and bonded by heat treatment in an N atmosphere. The wafer on which the pMOS is formed is polished and grinded from the rear. Hence it is made possible to apply a suitable semiconductor substrate to each kind of element, and to combine the substrates on which elements are previously formed.

20. 发明专利

JPH056894A METHOD AND APPARATUS FOR HEAT TREATING 失效
公开(公告)号：JPH056894A
公开(公告)日：1993-01-14
申请号：JP29272591
申请日：1991-11-08
申请人： TOSHIBA CORP , TEL SAGAMI LTD
发明人： YAMABE KIKUO , IMAI KEITAROU , OKUMURA KATSUYA , NAKAO MASARU , UENO MASAMITSU
IPC分类号： H01L21/324 , C30B31/12 , C30B31/14 , H01L21/22 , H01L21/31 , H01L21/673 , H01L21/683
摘要： PURPOSE:To suppress a temperature difference in a base to be treated, occurring when a plurality of bases to be treated, mounted perpendicularly to a heater and parallel to each other, are raised or lowered at a temperature, and to prevent a slip due to a thermal distortion, occurrences of a defect and a warpage of a crystal, etc. CONSTITUTION:In a heat treating apparatus having a heating chamber 11 in which predetermined gas is introduced, a heater 14 mounted around the chamber 11 and a jig 13 disposed in the chamber 11 to support a plurality of bases 12 to be treated parallel to each other, the jig 13 is formed of a ringlike tray for holding the bases 12 at its periphery, and the thickness of the tray is formed constantly or thicker at the outer peripheral side than at the inner peripheral side.

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