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1. 发明专利

JPH07273100A METHOD AND APPARATUS FOR HEAT-TREATMENT OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH07273100A
公开(公告)日：1995-10-20
申请号：JP8374594
申请日：1994-03-31
申请人： TOSHIBA CORP
发明人： YAMAMOTO AKITO , MIKATA YUICHI , YAMABE KIKUO
IPC分类号： H01L21/22 , H01L21/31 , H01L21/324
摘要： PURPOSE:To elevate the temperature of a semiconductor substrate to a target temperature for a heat-treatment without declining a temperature rising speed and cool the substrate with a high cooling speed by a method wherein heat radiation applied to the substrate is reduced before the substrate temperature reaches the target temperature for the heat-treatment. CONSTITUTION:The distance D between a semiconductor substrate 14 and a heating unit 11 is gradually reduced with a certain speed from the maximum distance D1. When a heating time reaches a time t1, the semiconductor 14 comes closest to the heating unit 11 with the minimum distance D2. After the heating time t1, the distance D2 is maintained for some time while a substrate temperature T keeps on rising with a certain rising speed and, at a time t2 when the substrate temperature T reaches a heat treatment temperature T3, the semiconductor substrate is kept away a little from the heating unit and the distance D3 at that time is maintained until the time reaches a time t3 when the heat-treatment is finished. Or, after the semiconductor substrate 14 reaches a position closet to the heating unit 11, a heat shielding plate 21 inserted between a treatment chamber 13 and the heating unit 11 is closed to reduce the heat radiation reaching the semiconductor substrate.

2. 发明专利

JPH05136153A SEMICONDUCTOR DEVICE AND ITS MANUFACTURE 失效
公开(公告)号：JPH05136153A
公开(公告)日：1993-06-01
申请号：JP29900391
申请日：1991-11-14
申请人： TOSHIBA CORP
发明人： NADAHARA SOUICHI , YAMABE KIKUO
IPC分类号： H01L21/322
摘要： PURPOSE:To obtain a semiconductor device and its manufacturing method wherein gettering is enabled without deteriorating element characteristics. CONSTITUTION:A poly-silicon film 2a doped with phosphorus wherein phosphorus concentration is about 10 atoms/cm or higher and the film thickness is about 400nm is deposited on the rear of silicon substrate 1b by a CVD method using SiH4 and PH3 gas, and sequentially low temperature heat treatment is performed, thereby segregating contaminants in an element region into the poly-silicon film 2a doped with phosphorus.

3. 发明专利

JPH04196587A MANUFACTURE OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH04196587A
公开(公告)日：1992-07-16
申请号：JP32847090
申请日：1990-11-28
申请人： TOSHIBA CORP
发明人： IWAI HIROSHI , MORIMOTO TOYOTA , MOMOSE HISAYO , YAMABE KIKUO , OZAWA YOSHIO
IPC分类号： H01L29/43 , H01L21/316 , H01L29/423 , H01L29/49 , H01L29/78
摘要： PURPOSE:To prevent a decline in the reliability of a semiconductor device caused by a gate insulating film by forming the gate insulating film through processes for depositing an insulating film on a semiconductor substrate, for heat-treating the insulating film, and for making the insulating film to contain nitrogen. CONSTITUTION:An oxide film 109 of silicon nitride is formed by making a silicon oxide film 107 to contain nitrogen by performing lamp heating in the atmosphere of dry oxygen after performing lamp heating in the atmosphere of a gas containing nitrogen atoms, such as ammonia gas. Then a gate oxide film 113 and gate electrode 115 are formed by working the oxide film 109 and a P polycrystalline silicon film 111. Since a gate insulating film 113 is formed by an LPD method, the stress applied to a substrate 101 from the film 113 becomes smaller as compared with the case where the gate insulating film 113 is formed by thermal oxidation.

4. 发明专利

JPH04101428A SEMICONDUCTOR DEVICE AND MANUFACTURE THEREOF 失效
公开(公告)号：JPH04101428A
公开(公告)日：1992-04-02
申请号：JP21820190
申请日：1990-08-21
申请人： TOSHIBA CORP
发明人： NADAHARA SOUICHI , TSUNODA HIROAKI , WATANABE MASAHARU , YAMABE KIKUO
IPC分类号： H01L21/8238 , H01L21/322 , H01L21/8242 , H01L27/092 , H01L27/10 , H01L27/108 , H01L27/148
摘要： PURPOSE:To allow a semiconductor element to be less affected by contamination by heavy metal, etc., for increasing an yield by forming a phosphorus diffusion layer in such high density as exceeds the solid solubility limit inside a semiconductor at the specified diffusion temperature. CONSTITUTION:On an n-type silicon substrate 11, a p-type well 12, field oxide film 13, silicon oxide film 14 and n type polysilicon film 15 are formed. Using the gate electrode 15 and field oxide film 13 as a mask, ions are injected to the substrate self-alignedly to form a p type layer 16, an n type layer 17 and source and drain regions for pM0S and nM0S. Then, a CVD oxide film 18 is formed on the whole surface. After an opening is made on the specified part of the oxide film 18, a second polysilicon film 19 is deposited on the whole surface of the device. Then, the whole body of the device is covered with an insulating film 20. After that, phosphorus is diffused from the rear surface of the substrate, for example, at 1000 deg.C for 60 minutes, to form a gettering site (a phosphorus diffusion layer) 21. In order to trap heavy metal, the device is subjected to a low-temperature treatment, for example, at 800 deg.C for 20 minutes or longer.

5. 发明专利

JPH01245515A MANUFACTURE OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH01245515A
公开(公告)日：1989-09-29
申请号：JP7185588
申请日：1988-03-28
申请人： TOSHIBA CORP
发明人： KAWAGUCHI HIDEKAZU , TSUNASHIMA YOSHITAKA , YAMABE KIKUO
IPC分类号： H01L21/22 , H01L21/225 , H01L21/316
摘要： PURPOSE:To improve the density of arsenic on the surface of a silicon substrate by a method wherein an arsenide compound is formed on the silicon oxide layer, on which arsenic is diffused, and on the interface of the silicon substrate at a specific temperature in inert gas atmosphere, the arsenic-silicon compound is oxidized at a specific temperature in an oxygen-containing atmosphere, and it is diffused on an arsenic-silicon substrate. CONSTITUTION:A silicon oxide layer of 100nm in thickness, having arsenic density of 1X10 atoms/cm , is deposited on a p-type silicon substrate by conducting an LPCVD method in which raw gas of Si (OC2H5)4 and As(OC2H5)4 is used. A heat-treatment is conducted thereon at 1000 deg.C for 90 minutes in an atmosphere of nitrogen only, and then they are heated at 1000 deg.C for 90 minutes in a nitrogen atmosphere containing 10% of oxygen. Subsequently, a silicon oxide film is removed using fluoric acid. The density of surface arsenic on the silicon substrate obtained is 3X10 atoms/cm , which is three times higher than the density obtained before using the atmosphere of nitrogen only.

6. 发明专利

JPH01216538A SEMICONDUCTOR DEVICE AND MANUFACTURE THEREOF 失效
公开(公告)号：JPH01216538A
公开(公告)日：1989-08-30
申请号：JP4152488
申请日：1988-02-24
申请人： TOSHIBA CORP
发明人： SATAKE HIDEKI , YAMABE KIKUO
IPC分类号： H01L21/302 , H01L21/3065 , H01L21/31 , H01L21/822 , H01L21/8242 , H01L27/04 , H01L27/10 , H01L27/108
摘要： PURPOSE:To improve reliability without blocking a high integration by setting the radius of curvature of the corners of the upper end of an abrupt step of a groove-dug type capacitor or the like to a predetermined range. CONSTITUTION:In a structure in which a step for forming a groove, a hole or the like is formed on the surface of a substrate and a conductor film is disposed through an insulating film on the region of this step, the corners of the upper end of the step are rounded at approx. 100-400Angstrom of radius of curvature. A sacrificing oxidation for rounding the corners of the step is preferably conducted by a low value such as 5-15Angstrom /min of oxidizing speed. The radius of curvature is ranged more preferably 100-200Angstrom and further preferably 140-200Angstrom . Thus, a breakdown strength deterioration due to an electric field concentration and an increase in a leakage current can be effectively suppressed, and a high integrated DRAM having high reliability can be obtained.

7. 发明专利

JPH01207926A TREATMENT APPARATUS FOR SEMICONDUCTOR WAFER 失效
公开(公告)号：JPH01207926A
公开(公告)日：1989-08-21
申请号：JP3342988
申请日：1988-02-16
申请人： TOSHIBA CORP
发明人： YAMABE KIKUO
IPC分类号： H01L21/22 , H01L21/31
摘要： PURPOSE:To make a temperature rise and fall quickly and avoid contamination of wafers caused by a heater by a method wherein a thermal capacity is reduced by eliminating a heat equalizer tube and the like and a reaction tube is composed of a double-layer tube. CONSTITUTION:In a treatment apparatus composed of a quartz tube 11, a heater 14 wound around the tube 11 and a reflector 15 covering the heater 14 so as to have a relatively small thermal capacity, the quartz tube 11 is composed of a double-layer tube. In other words, the quartz tube 11 which is a reaction tube has a double-layer structure composed of an inner tube 111 as shown in the figure and an outer tube 112 and gas introducing tubes 12 and 13 are linked with the inner tube 111 and the outer tube 112 respectively. With this constitution, a thermal treatment can be performed under a balanced state and, moreover, as a thermal capacity is reduced, a temperature can be made to rise and fall quickly. Further, by making predetermined gas flow through the outer tube 112 of the double-layer quartz tube 11, contamination of semiconductor wafers caused by the heater can be avoided.

8. 发明专利

JPS6386449A MANUFACTURE OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS6386449A
公开(公告)日：1988-04-16
申请号：JP22972686
申请日：1986-09-30
申请人： TOSHIBA CORP
发明人： YAMABE KIKUO
IPC分类号： H01L21/76
摘要： PURPOSE:To relax the reaction due to the density change of an Si oxide film buried in a groove, to inhibit a crystal defect from generating in a substrate and to contrive the improvement of characteristics of an element by a method wherein the groove is formed in the surface of the Si substrate and after the Si oxide film is buried in the groove by an adhesion method, a head treatment is once performed for at least prescribed seconds or more at a prescribed temperature or more before the following thin film forming process. CONSTITUTION:An Si substrate 1 is prepared, the whole surface is subjected to reactive ion etching (RIE) using a CVD oxide film 2 as a mask and a groove 3 having a vertical wall is formed. Then, an Si oxide film 4 is buried in the groove by a CVD method. Subsequently, a thermal treatment is performed for 5 seconds or more in a vapor-including atmosphere at a temperature of 1050 deg.C or more. After that, the Si oxide film 4 is etched back by an RIE method and the Si substrate surface of an element forming region is exposed. Moreover after this, a transistor is formed according to a manufacturing process including a general thin film forming process. Thereby, the stress due to the density change of the Si oxide film buried in the groove can be relaxed.

9. 发明专利

JPS6345848A MANUFACTURE OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS6345848A
公开(公告)日：1988-02-26
申请号：JP18853986
申请日：1986-08-13
申请人： TOSHIBA CORP
发明人： IMAI KIYOTAROU , YAMABE KIKUO
IPC分类号： H01L21/316 , H01L21/31 , H01L21/822 , H01L21/8242 , H01L27/04 , H01L27/10
摘要： PURPOSE:To form a third thermal oxide film in even thickness with a rugged corner rounded by a method wherein a first thermal oxide film is formed on the rugged surface of Si and after partially removing the oxide film by etching process, a second thermal oxide film is formed. CONSTITUTION:The first thermal oxide film 5 is formed on the rugged surface of Si 1 to be partly removed by etching process. At this time, the thermal oxide film at a corner A becomes extremely thin or the Si surface at the same part is exposed to atmosphere. Next, when another oxide film 6 is formed below the film 5 by the second thermal oxidation, the thermal oxidation at the corner A is accelerated making the angular part A round. After entirely removing the oxide films 5, 6, the third thermal oxide film can be formed on the surface of Si 1 to form the other oxide film in even thickness on the rugged surface of Si 1. When this oxide film is applied to the oxide film formed into a grooved type capacitor of a DRAM, the breakdown strength at the corner can be prevented from deteriorating, enabling a MOS capacitor with the least leakage current to be produced.

10. 发明专利

JPS61276226A MANUFACTURE OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS61276226A
公开(公告)日：1986-12-06
申请号：JP11638485
申请日：1985-05-31
申请人： TOSHIBA CORP
发明人： IMAI KEITAROU , YAMABE KIKUO
IPC分类号： H01L21/822 , H01L21/31 , H01L21/316 , H01L27/04
摘要： PURPOSE:To form an oxide film having superior insulation characteristics on the surface of the silicon substrate, which has a solid configuration, of a silicon semiconductor element and to improve the reliability of the element by a method wherein a thermal oxidation is performed to the silicon substrate at a specific temperature, an oxide film of a specific thickness is formed and after the oxide film is removed, the desired oxide film is formed. CONSTITUTION:A thermal oxidation is first performed to the surface of a silicon substrate 11 having a solid configuration at 900 deg.C or more, an oxide film 16 of 100Angstrom or less is formed and after this oxide film is removed, the desired oxide film 17 is formed. For example, an oxide film is adhered on the silicon substrate 11, part of the oxide film, which is located on the element forming region, is removed by performing a normal photo etching and masking materials 12 are formed. Then, an anisotropic etching is vertically performed on the silicon substrate 11 by an RIE using the same masking materials 12 as masks and a groove part 13 is formed. After that, the masking materials 12 are removed, a thermal oxidation is performed once at 900 deg.C or more in an oxidizing atmosphere and after the oxide film 16 of 100Angstrom or more and 500Angstrom or less is formed, the oxide film 16 is etched away and coner parts 14 and 15 in the groove part 13 are made round. After that, the gate oxide film 17 and a gate electrode 18 are formed and the grooved capacitor is manufactured.

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