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1. 发明专利

JP2014165404A Semiconductor device and method of manufacturing the same 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2014165404A
公开(公告)日：2014-09-08
申请号：JP2013036470
申请日：2013-02-26
申请人： Toshiba Corp , 株式会社東芝
发明人： MOROOKA SATORU , OGURO TATSUYA , MOMOSE HISAYO , FUKASE KAZUYA
IPC分类号： H01L29/786 , H01L21/28 , H01L21/283 , H01L21/768 , H01L23/532 , H01L29/417
CPC分类号： H01L29/7869 , H01L29/42384 , H01L29/45 , H01L29/4908 , H01L29/66969 , H01L29/78603 , H01L29/78636
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device that allows stabilizing the characteristics and to provide a method of manufacturing the same.SOLUTION: A semiconductor device includes a first electrode, an oxide semiconductor film, an insulating film, a first protection film, a second electrode, and a third electrode. The oxide semiconductor film is provided above the first electrode. The oxide semiconductor film has a first surface on the first electrode side and a second surface on the opposite side of the first surface. The insulating film is provided between the first electrode and the oxide semiconductor film. The first protection film has a first film provided between the insulating film and the first surface; and a second film provided on the second surface. The first protection film prevents a material including hydrogen from intruding into the inner side from the outer side of the oxide semiconductor film. The second electrode is electrically connected to the oxide semiconductor film. The third electrode is electrically connected to the oxide semiconductor film.
摘要翻译：要解决的问题：提供允许稳定特性并提供其制造方法的半导体器件。解决方案：半导体器件包括第一电极，氧化物半导体膜，绝缘膜，第一保护膜，第二电极和第三电极。氧化物半导体膜设置在第一电极的上方。氧化物半导体膜具有第一电极侧的第一表面和与第一表面相对的第二表面。绝缘膜设置在第一电极和氧化物半导体膜之间。第一保护膜具有设置在绝缘膜和第一表面之间的第一膜; 以及设置在第二表面上的第二膜。第一保护膜防止包含氢的材料从氧化物半导体膜的外侧侵入内侧。第二电极与氧化物半导体膜电连接。第三电极与氧化物半导体膜电连接。

2. 发明专利

JPH09252121A SEMICONDUCTOR DEVICE AND ITS MANUFACTURING METHOD 失效
公开(公告)号：JPH09252121A
公开(公告)日：1997-09-22
申请号：JP5931496
申请日：1996-03-15
申请人： TOSHIBA CORP
发明人： IWAI HIROSHI , MOMOSE HISAYO
IPC分类号： H01L29/78 , H01L21/28 , H01L21/336
摘要： PROBLEM TO BE SOLVED: To provide a minute gate electrode in an MOSFET at low cost by using an inexpensive manufacturing apparatus. SOLUTION: An insulating film 4 with a vertical side face is formed on a semiconductor substrate 1, and a gate insulating film 3 adjoining the insulating film 4 is formed thereto. A polycrystalline silicon is deposited along the side face of the insulating film 4 on the gate insulating film 3 and molded so as to form a gate electrode 5. An arsenic ion 6 is doped into the semiconductor substrate 1 through the gate insulating film 3 to form an arsenic diffusion layer 8. A solid phase diffusion step with phosphorus onto the insulating film 4 is carried out to form a gate electrode 5 having minute channel length. At the same time a phosphorus diffusion layer 7 as a source region and an arsenic diffusion layer 8 as a drain region are formed with the gate electrode 5 in between.

3. 发明专利

JPH0461318A SEMICONDUCTOR DEVICE AND ITS MANUFACTURE 失效
公开(公告)号：JPH0461318A
公开(公告)日：1992-02-27
申请号：JP17210890
申请日：1990-06-29
申请人： TOSHIBA CORP
发明人： KANBAYASHI SHIGERU , MOMOSE HISAYO , KAWAGUCHI HIDEKAZU , KENMOCHI MASAHITO , MIZUSHIMA ICHIRO
IPC分类号： H01L21/20 , H01L21/324
摘要： PURPOSE:To reduce the characteristic fluctuation of a semiconductor device by crystallizing an amorphous semiconductor by utilizing solid phase growth by repeating short-time heat treatment on an amorphous semiconductor film for several times, with each heat treatment being shorter in time than the latent period of the solid phase growth. CONSTITUTION:After a desired element area is formed in a p-type silicon substrate 20, an oxide and polycrystalline silicon films 21 and 22' are successively formed on the substrate by CVD methods. At the time of forming the films 21 and 22', small holes are formed through the silicon film 21 so that the polycrystalline silicon film 22' can come into contact with the substrate 20 and the contact areas are used as seed crystals. The silicon ions are implanted twice under such conditions that the accelerating voltages are respectively set at 50keV and 120keV and the dozing quantities are respectively set at 2.5X10 cm and 5.4X10 cm . Thereafter, the amorphous silicon film 22 thus formed is repeatedly heated to 610 deg.C for 10 hours each and a recrystallized polycrystalline silicon film 23 is obtained.

4. 发明专利

JPH03129774A SEMICONDUCTOR DEVICE AND MANUFACTURE THEREOF 失效
公开(公告)号：JPH03129774A
公开(公告)日：1991-06-03
申请号：JP31443889
申请日：1989-12-05
申请人： TOSHIBA CORP
发明人： MOMOSE HISAYO , IWAI HIROSHI , TAKAGI SHINICHI , KITAGAWA SATORU , YAMABE KIKUO
IPC分类号： H01L29/78 , H01L21/8238 , H01L27/092
摘要： PURPOSE:To enhance breakdown strength of gate and to prevent lowering of mobility of carrier by specifying the concentration of nitrogen atom in the vicinity of interface between a gate insulating film and a semiconductor layer. CONSTITUTION:In a semiconductor device comprising gate electrodes 54, 55 formed on a semiconductor layer of one conductivity through a gate insulating film 43 and source.drain regions of reverse conductivity formed at the opposite sides of the gate electrode, the gate insulating film 43 is formed such that the concentration of nitrogen atom in the vicinity of the interface to the semiconductor layer is equal to or higher than 1atom.% while lower than 10atom.%. Preferably, the oxide film 43 is as thick as a gate oxide film 42 or thinner than half of the thickness of the gate oxide film 42. It is because a thick oxide film 43 causes considerable deformation of the gate electrode to provide a bird beak below the electrode, whereas a thinner gate oxide film 43 can not feed sufficient nitrogen into an oxide film below the gate electrode. Upon finish of oxide film forming process, heating with lamp is carried out for 60sec at a temperature of 1050 deg.C in an environment containing such gas as ammonia, which contains nitrogen atoms, thus forming an after oxide film 44 containing nitrogen.

5. 发明专利

JP2014170841A Semiconductor device and method of manufacturing the same 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2014170841A
公开(公告)日：2014-09-18
申请号：JP2013041994
申请日：2013-03-04
申请人： Toshiba Corp , 株式会社東芝
发明人： MOROOKA SATORU , OGURO TATSUYA , MOMOSE HISAYO , FUKASE KAZUYA
IPC分类号： H01L29/786 , G02F1/1368 , H01L21/28 , H01L21/336 , H01L29/417 , H01L51/50
CPC分类号： H01L29/7869 , H01L29/42384 , H01L29/45 , H01L29/78603
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device that allows improving the characteristics and to provide a method of manufacturing the same.SOLUTION: A semiconductor device includes a first electrode, an oxide semiconductor film, an insulating film, a second electrode, and a third electrode. The oxide semiconductor film has a first region, a second region, a third region, a fourth region, and a fifth region that are arranged in one direction. The insulating film is provided between the oxide semiconductor film and the first electrode. The second electrode is provided on the second region and is in contact with the second region by using the entire top surface of the second region as a contact surface. The third electrode is provided on the fourth region and is in contact with the fourth region by using the entire top surface of the fourth region as a contact surface. The oxygen concentration of the second region is lower than that of the third region. The oxygen concentration of the fourth region is lower than that of the third region.
摘要翻译：要解决的问题：提供一种能够提高特性并提供其制造方法的半导体器件。解决方案：半导体器件包括第一电极，氧化物半导体膜，绝缘膜，第二电极和第三电极。氧化物半导体膜具有沿一个方向排列的第一区域，第二区域，第三区域，第四区域和第五区域。绝缘膜设置在氧化物半导体膜和第一电极之间。第二电极设置在第二区域上并且通过使用第二区域的整个顶表面作为接触表面与第二区域接触。第三电极设置在第四区域上，并且通过使用第四区域的整个顶表面作为接触表面与第四区域接触。第二区域的氧浓度低于第三区域的氧浓度。第四区域的氧浓度低于第三区域的氧浓度。

6. 发明专利

JP2012191097A Solid-state imaging device 审中-公开
标题翻译：固态成像装置
公开(公告)号：JP2012191097A
公开(公告)日：2012-10-04
申请号：JP2011055031
申请日：2011-03-14
申请人： Toshiba Corp , 株式会社東芝
发明人： MOMOSE HISAYO
IPC分类号： H01L31/10 , H01L27/146
CPC分类号： H01L27/14607 , H01L27/1461 , H01L27/14625 , H01L27/14685 , H01L31/109
摘要： PROBLEM TO BE SOLVED: To provide a solid-state imaging device that can, for example, improve photoelectric conversion efficiency and reduce undesirable current due to crystal defect.SOLUTION: A solid-state imaging device comprises a photodiode. In the photodiode, a first-conductivity-type region and a second-conductivity-type region are joined. The first-conductivity-type region has a first semiconductor region and a plurality of second semiconductor regions. The first semiconductor region is made from a material containing Si as a main component. Each of the plurality of second semiconductor regions is made from a material containing SiGe(0
摘要翻译：解决的问题：提供一种可以例如提高光电转换效率并减少由于晶体缺陷引起的不期望的电流的固态成像器件。解决方案：固态成像装置包括光电二极管。在光电二极管中，接合第一导电型区域和第二导电型区域。第一导电型区域具有第一半导体区域和多个第二半导体区域。第一半导体区域由含有Si作为主要成分的材料制成。多个第二半导体区域中的每一个由含有Si x的材料制成，（x <1≤x≤1））作为主要组成部分。多个第二半导体区域中的每一个在第一半导体区域上以岛状排列。版权所有（C）2013，JPO＆INPIT

7. 发明专利

JPH09252134A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH09252134A
公开(公告)日：1997-09-22
申请号：JP5974796
申请日：1996-03-15
申请人： TOSHIBA CORP
发明人： MOMOSE HISAYO , IWAI HIROSHI
IPC分类号： H01L29/786
摘要： PROBLEM TO BE SOLVED: To realize structure in fine channel length by forming an insular first semiconductor layer in a partial region on an SOI substrate, a second semiconductor layer on the first semiconductor layer and a third semiconductor layer having the same conductivity type as the first semiconductor layer on the second semiconductor layer and forming a gate electrode section to a part of a side face through an insulating film. SOLUTION: A semiconductor layer as a drain layer 4 is formed onto a silicon substrate 1. A semiconductor layer as a channel layer 5 is formed. A semiconductor layer as a source layer 6 is shaped. A gate insulating film 7 is formed onto one surfaces of the side faces of each layer of the drain layer 4, the channel layer 5 and the source layer 6, and a gate electrode 8 is formed to the upper section of the gate insulating film 7. Accordingly, the channel length of a MOS transistor can be controlled by the film thickness of silicon epitaxial growth, the MOS transistor having gate length finer than a conventional MOS transistor can be realized, and a device having high driving force can be acquired.

8. 发明专利

JPH08139327A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH08139327A
公开(公告)日：1996-05-31
申请号：JP25813295
申请日：1995-09-11
申请人： TOSHIBA CORP
发明人： MOMOSE HISAYO , IWAI HIROSHI , SAITO MASANOBU , OGURO TATSUYA , ONO TAMASHIRO , YOSHITOMI TAKASHI , NAKAMURA SHINICHI
IPC分类号： H01L29/78 , H01L21/8238 , H01L27/092
摘要： PURPOSE: To reduce the tunnel current by forming a gate electrode through an insulation film on a first conductivity type semiconductor substrate and forming a second conductivity type source-drain regions at both sides of a channel forming region right beneath the gate electrode with the thickness of the insulation film and gate length of the gate electrode below specified values. CONSTITUTION: A gate electrode 2 has a gate length Lg equal to the length direction of a channel forming region and thickness Tox of a gate insulator film 3 is set to 0.3μm or less and the thickness of the gate insulator 3 Tox is made than 2.5nm, respectively. The gate length dependence of a tunnel current 1g flowing to the gate is stabilized when it is less than 0.5μm at Lg of 0.3 or less, gate length W=10μm and oxide film thickness Tox=1.5nm and less than 0.1 at Tox=1.8nm. If Lg=0.3μm is exceeded, the gate current rapidly increases. Hence the gate current can be reduced by reduced Lg to 0.3μm or less.

9. 发明专利

JPH08139324A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH08139324A
公开(公告)日：1996-05-31
申请号：JP21682795
申请日：1995-07-12
申请人： TOSHIBA CORP
发明人： MOMOSE HISAYO , IWAI HIROSHI , SAITO MASANOBU , OGURO TATSUYA , ONO TAMASHIRO , YOSHITOMI TAKASHI , NAKAMURA SHINICHI
IPC分类号： H01L29/78 , H01L21/336 , H01L27/06
摘要： PURPOSE: To improve reliability under hot carrier stress by forming a gate electrode having a specified gate length via an insulation film of a specified thickness on a semiconductor substrate. CONSTITUTION: With respect to the dependency of transconductance deterioration upon gate oxide film thickness under hot carrier stress, the deterioration of mutual conductance gm when the thickness of gate oxide film 3 is less than 2.5mm becomes one/self of the amount of deterioration for the case of 3nm which was conventionally said to be the limit for the occurrence of tunnel current, and the life of transistor is more than donbled. Moreover, if it is used under 2.0nm, then the life of transistor is more than tripled. Where the thickness of gate oxide film 3 is less than To×2nm (less than 2.5nm, but less than 2.0nm is more desired), it becomes less than 10% when gate length Lg=0.10μm and less than 6% when Lg=0.14μm. Therefore, by reducing the gate oxide film 3 (insulation film) to less than 2.5nm, the reliability under the hot carrier stress can be enhanced.

10. 发明专利

JPH04196587A MANUFACTURE OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH04196587A
公开(公告)日：1992-07-16
申请号：JP32847090
申请日：1990-11-28
申请人： TOSHIBA CORP
发明人： IWAI HIROSHI , MORIMOTO TOYOTA , MOMOSE HISAYO , YAMABE KIKUO , OZAWA YOSHIO
IPC分类号： H01L29/43 , H01L21/316 , H01L29/423 , H01L29/49 , H01L29/78
摘要： PURPOSE:To prevent a decline in the reliability of a semiconductor device caused by a gate insulating film by forming the gate insulating film through processes for depositing an insulating film on a semiconductor substrate, for heat-treating the insulating film, and for making the insulating film to contain nitrogen. CONSTITUTION:An oxide film 109 of silicon nitride is formed by making a silicon oxide film 107 to contain nitrogen by performing lamp heating in the atmosphere of dry oxygen after performing lamp heating in the atmosphere of a gas containing nitrogen atoms, such as ammonia gas. Then a gate oxide film 113 and gate electrode 115 are formed by working the oxide film 109 and a P polycrystalline silicon film 111. Since a gate insulating film 113 is formed by an LPD method, the stress applied to a substrate 101 from the film 113 becomes smaller as compared with the case where the gate insulating film 113 is formed by thermal oxidation.

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