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1. 发明专利

JP2004289169A Semiconductor device and its manufacturing method 有权
公开(公告)号：JP2004289169A
公开(公告)日：2004-10-14
申请号：JP2004139906
申请日：2004-05-10
申请人： Toshiba Corp , 株式会社東芝
发明人： OKADA TAKAKO , KANBAYASHI SHIGERU , YABUKI SO , ONGA SHINJI , TSUNASHIMA YOSHITAKA , MIKATA YUICHI , OKANO HARUO
IPC分类号： H01L21/331 , H01L21/20 , H01L21/329 , H01L21/822 , H01L21/8234 , H01L21/8249 , H01L27/04 , H01L27/06 , H01L27/08 , H01L27/088 , H01L29/732 , H01L29/78
摘要： PROBLEM TO BE SOLVED: To provide a single crystal and a polycrystal having proper crystallinity at low temperature and to provide a semiconductor device having high reliability by using a solid phase growing method. SOLUTION: In order to deposit an amorphous semiconductor thin film on a substrate or an insulating film, particularly, the amorphus semiconductor thin film is formed so that a mean atomic interval distribution of the amorphous film made of a main element constituting the film substantially coincides with that of the single crystal, recrystallization energy is imparted to the amorphous semiconductor thin film, and a solid phase growth is performed to form a single crystal semiconductor thin film 3. COPYRIGHT: (C)2005,JPO&NCIPI

2. 发明专利

JP2006196908A Semiconductor device manufacturing method, manufacturing equipment, simulation method, and simulator 有权
标题翻译：半导体器件制造方法，制造设备，仿真方法和仿真器
公开(公告)号：JP2006196908A
公开(公告)日：2006-07-27
申请号：JP2006007760
申请日：2006-01-16
申请人： Toshiba Corp , 株式会社東芝
发明人： ONGA SHINJI , OKADA TAKAKO , TOMITA HIROSHI , YAMABE KIKUO , OKANO HARUO
IPC分类号： H01L21/00 , G06F17/50 , G06F19/00 , H01L21/02 , H01L21/316 , H01L21/336 , H01L21/76 , H01L21/8246 , H01L27/105 , H01L29/78
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device manufacturing method which can proceed a semiconductor device manufacturing process, without a test piece, as desired process or while correcting the process. SOLUTION: The semiconductor device manufacturing method, made up of a plurality of processes, includes a process to obtain a real observation data in at least one of the plurality of processes, a process of obtaining a forecasting data in at least one in of the plurality of processes by an abinitio molecular dynamics process simulator or a molecular dynamics simulator provided with an experimental potential, a process of relatively checking the forecast data and actual observed data in real time successively, and a process of correcting the manufacturing process factors in real time successively, when a significant difference has been recognized between the set value of the manufacturing process factor and the plurality of manufacturing process factors predicted from the real observed data. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供一种半导体器件制造方法，其可以根据期望的工艺进行半导体器件制造工艺，而不需要测试片，或者在校正工艺时。解决方案：由多个处理组成的半导体器件制造方法包括在多个处理中的至少一个中获得真实观测数据的处理，获得至少一个处理中的预测数据的处理的分子动力学过程模拟器或具有实验潜力的分子动力学模拟器的多个过程，连续相对地检查预测数据和实际观测数据的过程，以及校正制造工艺因素的过程当在制造工艺因素的设定值和从实际观察数据预测的多个制造工艺因素之间已经识别出显着差异时，依次实时地进行。版权所有（C）2006，JPO＆NCIPI

3. 发明专利

JP2006013525A Manufacturing method of semiconductor apparatus, manufacturing apparatus, simulation method and simulator 审中-公开
标题翻译：半导体装置的制造方法，制造装置，模拟方法和模拟器
公开(公告)号：JP2006013525A
公开(公告)日：2006-01-12
申请号：JP2005200821
申请日：2005-07-08
申请人： Toshiba Corp , 株式会社東芝
发明人： ONGA SHINJI , OKADA TAKAKO , TOMITA HIROSHI , YAMABE KIKUO , OKANO HARUO
IPC分类号： H01L29/78 , H01L21/00 , H01L21/02 , H01L21/336
摘要： PROBLEM TO BE SOLVED: To provide a manufacturing method of a semiconductor apparatus which enables a semiconductor apparatus manufacturing process to be proceeded without a test piece as a desired process or while amendments being effected. SOLUTION: In a manufacturing method of a semiconductor apparatus comprising a plurality of processes, actual observation data in at least one of the plurality of processes is obtained. Prediction data in at least one of the plurality of processes is obtained by an abinitio molecular dynamics process simulator or a molecular dynamics simulator provided with empirical potential. Then, the prediction data and the actual observation data are compared and tested successively in an actual time. When a significant difference is recognized between a set value of a manufacturing process factor and a factor of the plurality of manufacturing processes gathered from the actual observation data according to the comparison and test, the manufacturing process factor is amended successively in an actual time. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供一种半导体装置的制造方法，其能够使半导体装置制造工艺在没有试件作为期望的工艺的情况下进行，或者在实施修改的同时进行。解决方案：在包括多个处理的半导体装置的制造方法中，获得多个处理中的至少一个中的实际观测数据。在多个过程中的至少一个过程中的预测数据通过具有经验潜力的分析动力学过程模拟器或分子动力学模拟器获得。然后，在实际时间中连续地比较和测试预测数据和实际观察数据。当根据比较和测试从制造过程因子的设定值和从实际观察数据收集的多个制造过程的因子之间识别出显着差异时，制造过程因素在实际时间中连续地被修改。版权所有（C）2006，JPO＆NCIPI

4. 发明专利

JP2004289168A Semiconductor device and its manufacturing method 审中-公开
公开(公告)号：JP2004289168A
公开(公告)日：2004-10-14
申请号：JP2004139905
申请日：2004-05-10
申请人： Toshiba Corp , 株式会社東芝
发明人： OKADA TAKAKO , KANBAYASHI SHIGERU , YABUKI SO , ONGA SHINJI , TSUNASHIMA YOSHITAKA , MIKATA YUICHI , OKANO HARUO
IPC分类号： H01L21/331 , H01L21/20 , H01L21/329 , H01L21/336 , H01L21/822 , H01L21/8234 , H01L21/8249 , H01L27/04 , H01L27/06 , H01L27/08 , H01L27/088 , H01L29/732 , H01L29/78 , H01L29/786
摘要： PROBLEM TO BE SOLVED: To provide a single crystal and a polycrystal having proper crystallinity at low temperature and to provide a semiconductor device having high reliability by using a solid phase growing method. SOLUTION: In order to deposit an amorphous semiconductor thin film on a substrate or an insulating film, particularly, the amorphus semiconductor thin film is formed so that a mean atomic interval distribution of the amorphous film made of a main element constituting the film substantially coincides with that of the single crystal, recrystallization energy is imparted to the amorphous semiconductor thin film, and a solid phase growth is performed to form a single crystal semiconductor thin film 3. COPYRIGHT: (C)2005,JPO&NCIPI

5. 发明专利

JP2009033189A Method of manufacturing semiconductor 有权
标题翻译：制造半导体的方法
公开(公告)号：JP2009033189A
公开(公告)日：2009-02-12
申请号：JP2008237034
申请日：2008-09-16
申请人： Toshiba Corp , 株式会社東芝
发明人： OKADA TAKAKO , KANBAYASHI SHIGERU , YABUKI SO , ONGA SHINJI , TSUNASHIMA YOSHITAKA , MIKATA YUICHI , OKANO HARUO
IPC分类号： H01L21/20 , H01L21/329 , H01L21/331 , H01L21/336 , H01L21/822 , H01L21/8222 , H01L21/8248 , H01L21/8249 , H01L27/04 , H01L27/06 , H01L29/73 , H01L29/78 , H01L29/786
摘要： PROBLEM TO BE SOLVED: To provide a single crystal and a polycrystal under low temperature, and to provide a highly reliable semiconductor device using solid phase growing method. SOLUTION: In the method of depositing an amorphous semiconductor thin film on a substrate or an insulation film, the average atomic distance distribution of the amorphous film comprising the main component of the film is almost the same as that of the single crystal. A recrystallization energy is applied to the amorphous film to form a single crystal semiconductor film 3 with solid phase growth. COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：在低温下提供单晶和多晶体，并提供使用固相生长方法的高度可靠的半导体器件。解决方案：在基板或绝缘膜上沉积非晶半导体薄膜的方法中，包含膜的主要成分的非晶膜的平均原子距离分布几乎与单晶相同。对非晶膜施加再结晶能，形成具有固相生长的单晶半导体膜3。版权所有（C）2009，JPO＆INPIT

6. 发明专利

JP2005354089A Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：JP2005354089A
公开(公告)日：2005-12-22
申请号：JP2005179939
申请日：2005-06-20
申请人： Toshiba Corp , 株式会社東芝
发明人： OKADA TAKAKO , KANBAYASHI SHIGERU , YABUKI SO , ONGA SHINJI , TSUNASHIMA YOSHITAKA , MIKATA YUICHI , OKANO HARUO
IPC分类号： H01L27/04 , H01L21/205 , H01L21/822
摘要： PROBLEM TO BE SOLVED: To provide a single crystal and a polycrystal having proper crystallinity at a low temperature and to provide a semiconductor device having high reliability by using a solid phase growing method. SOLUTION: In order to deposit an amorphous semiconductor thin film on a substrate or an insulating film, particularly, the amorphus semiconductor thin film is formed so that a mean atomic interval distribution of the amorphous film made of a main element constituting the film substantially coincides with that of the single crystal, recrystallization energy is imparted to the amorphous semiconductor thin film, and a solid phase growth is performed to form a single crystal semiconductor thin film 3. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供在低温下具有适当结晶度的单晶和多晶，并通过使用固相生长方法提供具有高可靠性的半导体器件。解决方案：为了在基板或绝缘膜上沉积非晶半导体薄膜，特别地，形成非晶半导体薄膜，使得由构成膜的主要元件制成的非晶膜的平均原子间隔分布基本上与单晶的一致，向非晶半导体薄膜赋予再结晶能，进行固相生长以形成单晶半导体薄膜3.（C）2006，JPO＆NCIPI

7. 发明专利

JP2002270478A ELECTRONIC CIRCUIT DESIGN SIMULATOR 审中-公开
公开(公告)号：JP2002270478A
公开(公告)日：2002-09-20
申请号：JP2001390195
申请日：2001-12-21
申请人： TOSHIBA CORP
发明人： OKADA TAKAKO
IPC分类号： H01L21/28 , G06F17/50 , H01L21/00 , H01L21/3205 , H01L21/82 , H01L23/52
摘要： PROBLEM TO BE SOLVED: To accurately simulate dynamic characteristics of three-dimensional ramp electronic device circuit including the area of transistor, wiring section, capacitor, and resistor. SOLUTION: An electronic device simulator comprises: a three-dimensional ramp device model; a three-dimensional viscoelasticity process simulation model; and a mutually connected material design model. The three-dimensional ramp device element model comprises: a Poisson equation model; an electron continuity equation model; a hole continuity equation; a Maxwell equation model; an eddy-current equation model; and an Ohm's law equation model. The simulator clarifies the three-dimensional characteristics of circuits and determines the circuit characteristics.

8. 发明专利

JPH0334544A MANUFACTURE OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH0334544A
公开(公告)日：1991-02-14
申请号：JP16956889
申请日：1989-06-30
申请人： TOSHIBA CORP
发明人： OKADA TAKAKO
IPC分类号： H01L21/76 , H01L21/316
摘要： PURPOSE:To relax a stress onto a silicon substrate when an oxide film for element isolation use is formed by a method wherein a silicon oxide film under a silicon nitride film is doped with boron so that this oxide film can have viscous fluidity. CONSTITUTION:A silicon oxide film 12 and a silicon oxide film 13 which contains boron at a high concentration are formed on a substrate 11 ; this assembly is left at a high temperature of 950 deg.C for one hour; the boron contained in the oxide film 13 is diffused to the thermal oxide film 12 at a lower layer. when the boron is diffused, a coefficient of viscosity of the thermal oxide film 12 is increased to ten times or higher. Then, the oxide film 13 is removed; a silicon nitride film 14 is formed. In addition, the silicon nitride film 14 and the silicon oxide film 12 are etched selectively by making use of a resist 15 as a mask; an opening part 16 is formed; after that, the resist 15 is removed. Then, the silicon substrate 11 where the opening part 16 has been exposed is oxidized by wet oxidation at 1000 deg.C; an oxide film 17 for element isolation use is formed; the silicon nitride film 14 is removed; a desired element is formed in an element formation region.

9. 发明专利

JPH0595000A MANUFACTURE OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH0595000A
公开(公告)日：1993-04-16
申请号：JP25554191
申请日：1991-10-02
申请人： TOSHIBA CORP
发明人： KUNISHIMA YOSHIKO , TSUNASHIMA YOSHITAKA , OKADA TAKAKO
IPC分类号： H01L21/322 , H01L21/336 , H01L29/78
摘要： PURPOSE:To enable a low concentration diffusion layer to be easily formed with excellent controllability and free from damage so as to realize a semiconductor device which is excellent in characteristic and reliability by a method wherein lattice defects are formed adjacent to a high concentration region which is formed comparatively deep, and impurities are controlled so as to be diffused from the high concentration region concerned toward the lattice defects. CONSTITUTION:An element isolation insulating film 12 is formed on a p-type silicon substrate 11, a silicon oxide film 13 is formed, and then a gate electrode 14 is provided. Thereafter, a silicon oxide film 15 is formed, a thin silicon nitride film 16 is formed adjacent to the gate electrode 14, a vacancy injected region 17 where a large number of vacancies are injected by nitriding is formed, and an n diffusion layer 19 is formed to serve as a source.drain region. Thereafter, the diffusion of impurities from the n diffusion layer 19 toward the vacancy injected region 17 is accelerated through a thermal treatment, whereby a n-type diffusion layer 17S of low concentration can be formed in a lateral direction by the side of the n diffusion layer 19. By this setup, a thin diffusion region of very accuracy can be formed high in controllability.

10. 发明专利

JPH0594958A MANUFACTURE OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH0594958A
公开(公告)日：1993-04-16
申请号：JP25554091
申请日：1991-10-02
申请人： TOSHIBA CORP
发明人： OKADA TAKAKO
IPC分类号： H01L21/265 , H01L21/326 , H01L21/336 , H01L29/78
摘要： PURPOSE:To enable a diffusion layer to be easily formed with excellent controllability by a method wherein lattice defects are generated so as to have a required concentration larger than a certain concentration where it is in a thermal equilibrium state before a thermal process is carried out for diffusion, and diffusion of impurities is controlled while an electrical field is applied. CONSTITUTION:An element isolation insulating film 2 is formed on the rear of a P-type silicon substrate 1, a phosphorus glass layer 3 which contains phosphorus high in concentration is formed, a silicide electrode 4 is formed in an opening formed at the center of the phosphorus glass layer 3. The silicide electrode 4 is also formed on the surface of the substrate 1, a voltage is applied between the electrodes 4 to enable arsenic ions to be diffused from an impurity region 5 formed on the surface by the introduction of arsenic ions. At this point, the substrate 1 is kept at a relatively low temperature of 850 deg.C, and impurities are controlled in diffusion through a high electric field over 10 V/cm in intensity and lattice defects. By this setup, a required diffusion layer high in controllability can be obtained.

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