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11. 发明专利

JP2006196926A Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：JP2006196926A
公开(公告)日：2006-07-27
申请号：JP2006108912
申请日：2006-04-11
申请人： Toshiba Corp , 株式会社東芝
发明人： USHIKU YUKIHIRO , MIZUNO TOMOHISA , YOSHIMI MAKOTO , TERAUCHI MAMORU , KAWANAKA SHIGERU
IPC分类号： H01L29/78 , H01L29/41
CPC分类号： H01L29/785
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device in which element characteristics can be improved. SOLUTION: The semiconductor device includes: a substrate 21 having a projecting semiconductor element region 23; a gate electrode formed on the upper and lateral surfaces of the element region 23; an insulating film 41 for covering the element region 23 and provided with a contact hole; and first and second contact wirings 43 for embedding a contact hole and coming in contact with the element region 23. In the element region 23, a source region 47 and a drain region 48 are spaced apart each other and come in contact with the first and the second contact wirings 43, respectively; at least one contact wiring 43 comes in contact with both a part of the upper surface and a part of the lateral surfaces of the element region 23; and the thickness of the source region 47 or the drain region 48 coming in contact with the contact wiring 43 is thicker at a position coming in contact with the contact wiring 43, as compared with a position not coming in contact with the contact wiring 43. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供可以提高元件特性的半导体器件。解决方案：半导体器件包括：具有突出的半导体元件区域23的衬底21; 形成在元件区域23的上表面和侧表面上的栅电极; 用于覆盖元件区域23并设置有接触孔的绝缘膜41; 以及用于嵌入接触孔并与元件区域23接触的第一和第二接触布线43.在元件区域23中，源极区域47和漏极区域48彼此间隔开并与第一和第二接触布线接触第二接触线43; 至少一个接触配线43与元件区域23的上表面的一部分和侧面的一部分接触; 与不与接触配线43接触的位置，与接触配线43接触的位置处，与接触配线43接触的源极区域47或漏极区域48的厚度较厚。版权所有（C）2006，JPO＆NCIPI

12. 发明专利

JP2004119884A Semiconductor device 审中-公开
公开(公告)号：JP2004119884A
公开(公告)日：2004-04-15
申请号：JP2002284331
申请日：2002-09-27
申请人： Toshiba Corp , 株式会社東芝
发明人： KAWANAKA SHIGERU , ARAI HIDEAKI
IPC分类号： H01L21/336 , H01L27/12 , H01L29/423 , H01L29/49 , H01L29/786
CPC分类号： H01L29/78615 , H01L29/42384 , H01L29/4908 , Y10S257/901
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device in which a potential of a body region is avoided from floating. SOLUTION: The semiconductor device includes an insulating film provided on a semiconductor substrate and a semiconductor layer provided on the insulating film. An element isolation insulating film isolating an element region is provided in the semiconductor layer. A first gate insulating film is provided on the semiconductor layer in the element region. A gate electrode is provided on the first gate insulating film. Source/drain diffusion layers are formed in the semiconductor layer sandwiching a channel region under the gate electrode therebetween. A potential applying part for sending a leakage current which controls the potential of the semiconductor layer comprises a second gate insulating film provided on the semiconductor layer in the element region and a conductive film provided on the second gate insulating film and connected to the gate electrode. The potential applying part is configured so that a leakage current larger than that through the first gate insulating film is sent. COPYRIGHT: (C)2004,JPO

13. 发明专利

JPH11330082A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH11330082A
公开(公告)日：1999-11-30
申请号：JP13713198
申请日：1998-05-19
申请人： TOSHIBA CORP
发明人： YAMADA TAKASHI , ARAI HIDEAKI , YOSHIMI MAKOTO , SHINO TOMOAKI , INO KAZUMI , KAWANAKA SHIGERU , FUSE TSUNEAKI , YOSHITOMI SADAYUKI
IPC分类号： H01L21/331 , H01L29/10 , H01L29/73
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device as a bipolar transistor which is able to obtain extremely good high frequency characteristics by reducing an intrinsic base width without increasing the base resistance. SOLUTION: An emitter region, an intrinsic base region (p) and a collector region (n ) are arranged on an insulation layer, and an intrinsic base region and a collector region are formed to have a projection part respectively which projects upward to a board surface. The projected part is made wider than the intrinsic base region. According to these features, superior high frequency characteristics can be realized by reducing a base resistance.

14. 发明专利

JPH11260830A BIPOLAR SEMICONDUCTOR DEVICE AND ITS MANUFACTURE 失效
公开(公告)号：JPH11260830A
公开(公告)日：1999-09-24
申请号：JP6367198
申请日：1998-03-13
申请人： TOSHIBA CORP
发明人： YAMADA TAKASHI , SHINO TOMOAKI , KAWANAKA SHIGERU , YOSHIMI MAKOTO , FUSE TSUNEAKI , TERAUCHI MAMORU , INOU KAZUMI
IPC分类号： H01L29/73 , H01L21/331 , H01L21/8249 , H01L27/06
摘要： PROBLEM TO BE SOLVED: To provide a bipolar semiconductor device which has satisfactory low base resistance and is capable of adequately restraining both the lowering of current amplification factor and deterioration of high frequency characteristic. SOLUTION: A semiconductor thin film which becomes an emitter region 3a and a base lead-out region 3b is formed by using different mask materials through different lithographic processes and a diffusion layer which forms each region is formed mutually self-aligned. A structure in which the emitter region 3a and the base lead-out region 3b approaching less than or equal to the base width is thereby made possible. Furthermore, since impurity introduction to a base lead-out region is carried out before the impurity introduction to the base and the emitter which prescribes the base width, impurity profile and base width of the emitter region 3a and the base region 4a can be set ideally.

15. 发明专利

JPH07249768A MIS TYPE SEMICONDUCTOR DEVICE AND ITS FABRICATION 失效
公开(公告)号：JPH07249768A
公开(公告)日：1995-09-26
申请号：JP4213694
申请日：1994-03-14
申请人： TOSHIBA CORP
发明人： KAWANAKA SHIGERU , USHIKU YUKIHIRO , YOSHIMI MAKOTO , MIZUNO TOMOHISA , TERAUCHI MAMORU
IPC分类号： H01L29/78 , H01L29/786
摘要： PURPOSE:To achieve low cut-off characteristics and high driving capacity equivalent to those of a conventional complete depletion type SOI MOSFET while solving the essential problem i.e., lowering of withstand voltage of drain and hump or hystresis in the characteristics of element. CONSTITUTION:The MIS type semiconductor device comprises a source-drain region provided in the semiconductor region 4 on the surface of a substrate 1 while being spaced apart from each other, a channel region formed in the source-drain region with protrusions and recesses being provided along a line connecting the source and drain regions, a first insulating film 2 embedded under the channel region while corresponding to the recess, a second insulating film 6 formed as a gate insulating film on the channel region, and a gate electrode 7 formed on the channel region through the second insulating film 6.

16. 发明专利

JP2012190913A Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：JP2012190913A
公开(公告)日：2012-10-04
申请号：JP2011051671
申请日：2011-03-09
申请人： Toshiba Corp , 株式会社東芝
发明人： SUGISAKI EMIKO , KAWANAKA SHIGERU , ADACHI KANNA
IPC分类号： H01L29/78 , H01L21/336 , H01L29/66 , H01L29/786
CPC分类号： H01L29/7391 , H01L29/0657 , H01L29/42312
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device that can surely perform an ON/OFF control in a vertical P-N junction.SOLUTION: A semiconductor device comprises: a semiconductor layer; a gate insulating film provided on the semiconductor layer; and a gate electrode provided on the gate insulating film. A first channel region of a first conductivity type is provided in a part of a surface of the semiconductor layer under the gate insulating film. A diffusion layer of a second conductivity type different from the first conductivity type is provided in the semiconductor layer below the first channel region, contacts the bottom of the first channel region in a substantially perpendicular to the surface of the semiconductor layer, and forms a P-N junction with the bottom of the first channel region. A drain of the first conductivity type and a source of the second conductivity type are each provided at both sides of the first channel region in the semiconductor layer. A sidewall insulating film coats the side surface of the first channel region at the diffusion layer side.
摘要翻译：要解决的问题：提供一种能够确定地在垂直P-N结中进行ON / OFF控制的半导体器件。解决方案：半导体器件包括：半导体层; 设置在半导体层上的栅极绝缘膜; 以及设置在栅极绝缘膜上的栅电极。第一导电类型的第一沟道区域设置在栅极绝缘膜下面的半导体层的表面的一部分中。与第一导电类型不同的第二导电类型的扩散层设置在第一沟道区下面的半导体层中，与第一沟道区的底部基本上垂直于半导体层的表面接触，形成PN 与第一通道区域的底部连接。第一导电类型的漏极和第二导电类型的源极分别设置在半导体层中的第一沟道区的两侧。侧壁绝缘膜在扩散层侧涂覆第一沟道区域的侧表面。版权所有（C）2013，JPO＆INPIT

17. 发明专利

JP2009267160A Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：JP2009267160A
公开(公告)日：2009-11-12
申请号：JP2008116204
申请日：2008-04-25
申请人： Toshiba Corp , 株式会社東芝
发明人： TATSUMURA KOSUKE , GOTO MASAKAZU , ICHIHARA REIKA , KOYAMA MASATO , KAWANAKA SHIGERU , NAKAJIMA KAZUAKI
IPC分类号： H01L21/8238 , H01L21/28 , H01L27/092 , H01L29/423 , H01L29/49 , H01L29/78 , H01L29/786
CPC分类号： H01L21/823828 , H01L21/823842 , H01L29/785
摘要： PROBLEM TO BE SOLVED: To provide a single metal CMISFET having high inversion layer carrier mobility.
SOLUTION: A semiconductor device includes a semiconductor substrate, and a p-channel MIS transistor and an n-channel MIS transistor which are formed on the semiconductor substrate. Each of the p-channel MIS transistor and the n-channel MIS transistor has a gate dielectric film formed on the semiconductor substrate and a gate electrode layer formed on the gate dielectric film. Bottom layers of the gate electrodes of the p-channel MIS transistor and the n-channel MIS transistor, which are brought into contact with at least the gate dielectric films, have the same composition including Ta and C, a mole ratio (Ta/(Ta+C)) of Ta to a total of C and Ta is larger than 0.5, and these bottom layers have the same orientation.
COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：提供具有高反转层载流子迁移率的单金属CMISFET。解决方案：半导体器件包括形成在半导体衬底上的半导体衬底和p沟道MIS晶体管和n沟道MIS晶体管。 p沟道MIS晶体管和n沟道MIS晶体管中的每一个具有形成在半导体衬底上的栅极电介质膜和形成在栅极电介质膜上的栅极电极层。与至少栅极电介质膜接触的p沟道MIS晶体管和n沟道MIS晶体管的栅电极的底层具有包括Ta和C的相同组成，摩尔比（Ta /（ Ta + C））至总共C和Ta大于0.5，这些底层具有相同的取向。版权所有（C）2010，JPO＆INPIT

18. 发明专利

JP2003188279A SEMICONDUCTOR MEMORY DEVICE AND ITS MANUFACTURING METHOD 审中-公开
公开(公告)号：JP2003188279A
公开(公告)日：2003-07-04
申请号：JP2001381458
申请日：2001-12-14
申请人： TOSHIBA CORP
发明人： KAWANAKA SHIGERU
IPC分类号： H01L29/78 , G11C11/405 , H01L21/8238 , H01L21/8242 , H01L21/84 , H01L27/08 , H01L27/092 , H01L27/108 , H01L27/11 , H01L27/12 , H01L29/786
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor memory device in which data can be stably written in a memory cell which does not need a capacitor and to provide a method for manufacturing the same. SOLUTION: The semiconductor memory device comprises a semiconductor layer 13 formed on an insulating film 12, and a memory cell array having a plurality of memory cells 10 in which first and second transistors Tr1, Tr2 formed in the semiconductor layer are connected in series, formed and disposed in a matrix state connected to a bit line BL in which one side of the cell is connected and a reference potential is imparted to other side. An element threshold voltage is changed by implanting/discharging a charge in or from a body region connected to the bit line BL of two partially depleted transistors connected in series with each other in response to data. COPYRIGHT: (C)2003,JPO

19. 发明专利

JP2002064206A SEMICONDUCTOR DEVICE AND ITS MANUFACTURING METHOD 失效
公开(公告)号：JP2002064206A
公开(公告)日：2002-02-28
申请号：JP2000301509
申请日：2000-09-29
申请人： TOSHIBA CORP
发明人： YAMADA TAKASHI , ARAI HIDEAKI , KAWANAKA SHIGERU
IPC分类号： H01L29/417 , H01L21/3205 , H01L21/331 , H01L21/768 , H01L21/8222 , H01L21/8234 , H01L21/8242 , H01L21/8248 , H01L21/8249 , H01L23/52 , H01L27/06 , H01L27/08 , H01L27/088 , H01L27/108 , H01L29/423 , H01L29/43 , H01L29/49 , H01L29/73 , H01L29/786
摘要： PROBLEM TO BE SOLVED: To miniaturize an element without changing a manufacturing pattern, maintain performance and enable manufacturing at a low cost. SOLUTION: In a semiconductor device, a semiconductor layer 2 is formed on an insulating film 1, and an arbitrary number of semiconductor elements are formed on the semiconductor layer 2. The semiconductor layer is provided with an element region 3 for forming the semiconductor elements and potential leading-out regions 4a, 4b as thin semiconductor films which are collectively formed in self-alignment manner to the element region 3 and thinner than the element region.

20. 发明专利

JP2001185556A SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR 失效
公开(公告)号：JP2001185556A
公开(公告)日：2001-07-06
申请号：JP36419799
申请日：1999-12-22
申请人： TOSHIBA CORP
发明人： KAWANAKA SHIGERU , ARAI HIDEAKI
IPC分类号： H01L29/73 , H01L21/331
摘要： PROBLEM TO BE SOLVED: To improve high-frequency characteristics of a lateral bipolar transistor. SOLUTION: In a manufacturing method of a bipolar transistor, in which an emitter region, a base region, a collector region are arranged in the crosswise direction on a semiconductor layer formed on an insulating film, an extracting electrode for applying the potential that in the past could not be applied to the base region is formed self-consistently, and the bipolar transistor with good controllability can be formed without increasing parasitic resistance by parasitic capacity.

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