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1. 发明专利

JP2006324472A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 审中-公开
公开(公告)号：JP2006324472A
公开(公告)日：2006-11-30
申请号：JP2005146404
申请日：2005-05-19
申请人： TOSHIBA CORP
发明人： FUSE TSUNEAKI , IDAKA YASUHITO
IPC分类号： H01L27/08 , H01L21/76 , H01L29/06
摘要： PROBLEM TO BE SOLVED: To improve the performance of a MOS transistor and obtain a high circuit integration degree by forming fine gates by using a conventional photolithography. SOLUTION: The semiconductor integrated circuit comprises a semiconductor substrate, desired conductivity type well regions formed on the semiconductor substrate, and a plurality of first conductivity type MOS transistors including gate electrodes and a source-drain layer on the well regions. At least one of the plurality of MOS transistors functions for isolating elements between the MOS transistors. COPYRIGHT: (C)2007,JPO&INPIT

2. 发明专利

JP2002135106A LEVEL CONVERSION CIRCUIT AND SEMICONDUCTOR INTEGRATED CIRCUIT 失效
公开(公告)号：JP2002135106A
公开(公告)日：2002-05-10
申请号：JP2000325047
申请日：2000-10-25
申请人： TOSHIBA CORP
发明人： OUCHI KAZUNORI , KAMEYAMA ATSUSHI , FUSE TSUNEAKI , YOSHIDA MASAKO
IPC分类号： G11C11/417 , G11C11/409 , H01L21/822 , H01L21/8238 , H01L27/04 , H01L27/092 , H03K19/00 , H03K19/0185
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit which converts a very small logic level of about 0.5 V into a 1 to 3 V of conventional logical level, and is low power consumption with a large allowance with respect to device characteristics, and further has a level conversion circuit that prevents deterioration of operational speed. SOLUTION: A semiconductor integrated circuit, of which each output of low voltage operation logic circuit and its logically converted output, is connected and driven to two outputs of a cross latch, which is composed of cross connection of two FETs via each gate grounded FET. Further two of the cross latch are set and a third cross latch (301, 302) is connected between the first and second output which are level converted by these two cross latches (the first and second cross latches).

3. 发明专利

JP2001274675A SEMICONDUCTOR INTEGRATED CIRCUIT 失效
公开(公告)号：JP2001274675A
公开(公告)日：2001-10-05
申请号：JP2000086385
申请日：2000-03-27
申请人： TOSHIBA CORP
发明人： KAMEYAMA ATSUSHI , FUSE TSUNEAKI , OUCHI KAZUNORI , YOSHIDA MASAKO
IPC分类号： G11C11/409 , H01L21/822 , H01L27/04 , H03K19/0185
摘要： PROBLEM TO BE SOLVED: To realize a semiconductor integrated circuit that includes a level conversion circuit having a high degree of permissibility of an element characteristic with low power consumption that converts a very small logic level such as about 0.5 V into about 1 V to 3 V being a conventional logic level. SOLUTION: The level conversion circuit is provided with a P-channel latch consisting of common gate P-channel MOSFETs 100, 101 and N-channel MOSFETs 102, 103 that receive complementary signals 10A, 10B from a logic circuit and of P-channel MOSFETs 104, 105 and with an N-channel latch consisting of N-channel MOSFETs 106, 107. Leading an output of the logic circuit operated at a low voltage and its inverted logic output to each latch via a common gate circuit can drive two FETs configuring each latch by complementary inputs so as to enhance the gain characteristic of each latch.

4. 发明专利

JPH10125925A SEMICONDUCTOR INTEGRATED CIRCUIT 失效
公开(公告)号：JPH10125925A
公开(公告)日：1998-05-15
申请号：JP28250796
申请日：1996-10-24
申请人： TOSHIBA CORP
发明人： YOSHIDA MASAKO , OWAKI YUKITO , FUSE TSUNEAKI
IPC分类号： H01L29/786
摘要： PROBLEM TO BE SOLVED: To make it possible to reduce more a parasitic capacitance in an SOI transistor and to speed up the operating speed of the SOI transistor. SOLUTION: The integrated circuit is one of a structure, wherein a CMOS circuit consisting of an N-channel MOS transistor 20 and a P-channel MOS transistor 30 is formed on an SOI substrate 10 with an Si layer 13 formed on an Si substrate 11 via an SiO2 film 12. In this case, the part, which is positioned under the formation region of the transistor 20, of the substrate 11 is formed into a p-type region 11a, the part, which is positioned under the formation region of the transistor 30, of the substrate 11 is formed into an n-type region 11b, a negative potential is applied to the region 11a and a positive potential is applied to the region 11b.

5. 发明专利

JPH09162408A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPH09162408A
公开(公告)日：1997-06-20
申请号：JP31780995
申请日：1995-12-06
申请人： TOSHIBA CORP
发明人： FUSE TSUNEAKI , OWAKI YUKITO
IPC分类号： H01L29/786 , H03K19/0948 , H03K19/20
摘要： PROBLEM TO BE SOLVED: To reduce the number of transistors constituting a basic gate, reduce the cost of a chip, and to reduce power consumption, relating to the device. SOLUTION: A logic circuit such as a 2-input NAND gate and a 2-input NOR gate, etc., is constituted. At this time, an nMOS transistor M11 formed an a silicon substrate on an insulation film is provided, and, a drain and a source of the nMOS transistor M11 are connected to an output terminal Y and an earth end Vss, respectively, and the first signal XA is inputted to the gate, and the second signal XB is inputted to a substrate area, and a resistance element 15 is connected between the drain of the M11 and a power supply end Vcc, and the first and second input signals XA and XB are combined for outputting a single logic signal.

6. 发明专利

JPH0955652A SEMICONDUCTOR INTEGRATED CIRCUIT 失效
公开(公告)号：JPH0955652A
公开(公告)日：1997-02-25
申请号：JP23162295
申请日：1995-09-08
申请人： TOSHIBA CORP
发明人： FUSE TSUNEAKI , OWAKI YUKITO , SHUDO YOKO
IPC分类号： H03K19/0175 , G11C11/407 , H03K19/0948
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit suitable for a higher speed operation by reducing a standby current without losing a circuit operation margin even when a low power supply voltage is employed. SOLUTION: This integrated circuit has a circuit array consisting of three stages of inverter circuits I (I1, I2, I3) each comprising a series connection of a P-channel MOS transistor(TR) Mp (Mp1, Mp2, Mp3) and an N-channel MOS TR Mn (Mn1, Mn2, Mn3). Each MOS TR is formed on an SOI substrate and an input terminal of the 1st stage inverter circuit I1 is connected to a base area of the MOS TRs Mp3, Mn3 being components of the 3rd stage inverter circuit 13.

7. 发明专利

JPH03283462A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH03283462A
公开(公告)日：1991-12-13
申请号：JP8111890
申请日：1990-03-30
申请人： TOSHIBA CORP
发明人： NAKANO HIROAKI , FUSE TSUNEAKI , HASEGAWA TAKEHIRO , SAKUI YASUSHI , WATANABE SHIGEYOSHI , MASUOKA FUJIO
IPC分类号： H01L27/082 , H01L21/8222 , H01L21/8242 , H01L27/108
摘要： PURPOSE:To lessen a bipolar transistor which composes a memory cell in collector current in operation by a method wherein the emitter of the bipolar transistor is lessened more in area as compared with a base contact so as to change a collector current Ico, and an avalanche multiplication phenomenon induced at a junction between a collector and a base is controlled. CONSTITUTION:An N -type forcedly plunged layer 22 is provided onto the surface of a P -type silicon substrate 21 so as to lessen a collector in resistance, and furthermore a P -type epitaxial silicon layer 23 is provided thereon. Phosphorus is introduced into the P -type silicon layer 23 to form an N-type well 24. A field oxide film 25 is formed on the surface, a polysilicon 27 is provided onto an opening provided between the oxide films 25 on a collector lead-out layer 26 deep enough to reach to the N -type forcibly plunged layer 22, and a P -type base region 28 is provided to another opening. An N -type emitter region 29 is formed formed on a part of the P -type base region 28, a thin oxide film 30 is formed on the surface of the substrate, and furthermore a polysilicon 32 is formed through the intermediary of the window of a CVD SiO2 film 31. A P -type layer 33 (outer base) is provided adjacent to the P -type base region 28.

8. 发明专利

JPH03283082A SEMICONDUCTOR STORAGE DEVICE 失效
公开(公告)号：JPH03283082A
公开(公告)日：1991-12-13
申请号：JP8112290
申请日：1990-03-30
申请人： TOSHIBA CORP
发明人： SAKUI YASUSHI , FUSE TSUNEAKI , HASEGAWA TAKEHIRO , WATANABE SHIGEYOSHI , MASUOKA FUJIO
IPC分类号： G11C11/405 , H01L21/8229 , H01L27/102
摘要： PURPOSE:To let a forward base current and a backward base current flow corresponding to a base potential by using a bipolar transistor controlling a voltage between a collector and an emitter so as to change the polarity of the base current with the increase of a voltage between a base and the emitter. CONSTITUTION:The bipolar transistor is used while setting a voltage VCE between the collector and the emitter corresponding to the base potential under the condition of IB

9. 发明专利

JPH02126720A TRANSISTOR CIRCUIT 失效
公开(公告)号：JPH02126720A
公开(公告)日：1990-05-15
申请号：JP28063588
申请日：1988-11-07
申请人： TOSHIBA CORP
发明人： FUSE TSUNEAKI
IPC分类号： H01L27/06 , H01L21/8249 , H03K17/567 , H03K19/08 , H03K19/0944
摘要： PURPOSE:To prevent the increase of the current consumption and the malfunction and to obtain a high action margin by providing a resistance element between the base and emitter of a transistor of an output circuit. CONSTITUTION:Between the base and emitter of a Tr Q1 of an output circuit 2 of a BiCMOS circuit combining a CMOSFET circuit and a bipolar transistor Tr, a resistance element R is connected. Thus, when the output of a CMOS gate comes to an 'H' level, after the output terminal of the circuit 2 rises up to VCC-phiBE by the Tr Q1, further, it is charged through a resistance element R and rises up to a power source potential VCC completely. When the output of the CMOS gate comes to an 'L' level, the Tr Q1 is turned off, a Tr Q2 is turned on, the output terminal is reduced to the phiBE, thereafter, further, completely falls through the resistance element R and an (n) channel MOSFETM2 in which the CMOS gate is turned on, to a ground potential VSS.

10. 发明专利

JPH021158A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH021158A
公开(公告)日：1990-01-05
申请号：JP15818888
申请日：1988-06-28
申请人： TOSHIBA CORP
发明人： SAKUI YASUSHI , FUSE TSUNEAKI , ARITOME SEIICHI , HASEGAWA TAKEHIRO , WATANABE SHIGEYOSHI , MASUOKA FUJIO , SESHIMO TOSHIKI , NITAYAMA AKIHIRO , HORIGUCHI FUMIO
IPC分类号： H01L29/73 , H01L21/331 , H01L21/8222 , H01L21/8249 , H01L27/06 , H01L27/10 , H01L29/72 , H01L29/732
摘要： PURPOSE:To realize a transistor whose base current has a negative region in addition to a conventional positive region and to realize high integration by a method wherein a collector-emitter voltage is set at a high voltage and a reverse base current, between a collector and 4 base, which is larger than a forward base current between the base and an emitter can flow to a base potential. CONSTITUTION:A bipolar transistor where a negative base current in addition to a positive base current can flow according to a base potential is used. That is to say, when a forward base current between a base and an emitter and a reverse base current between a collector and the base are designated as IBE and ICB, respectively, the bipolar transistor whose collector-emitter voltage VCE is set so as to become IBE

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