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1. 发明专利

JP2015056619A 半導体装置有权
标题翻译：半导体器件
公开(公告)号：JP2015056619A
公开(公告)日：2015-03-23
申请号：JP2013190889
申请日：2013-09-13
申请人：株式会社東芝 , Toshiba Corp
发明人： KONDO YOSHIYUKI , GOTO MASAKAZU , KAWANAKA SHIGERU , MIYATA TOSHINORI
IPC分类号： H01L21/336 , H01L29/66 , H01L29/78 , H01L29/786
CPC分类号： H01L29/66977 , H01L29/165 , H01L29/66356 , H01L29/66659 , H01L29/7391 , H01L29/7833
摘要：【課題】電源電圧を低く抑えることができるトンネル型半導体装置を提供する。【解決手段】本実施形態による半導体装置は、半導体層を備える。ゲート絶縁膜は、半導体層表面上に設けられている。ゲート電極は、半導体層上にゲート絶縁膜を介して設けられている。第1導電型のドレイン層は、ゲート電極の一端側にある半導体層内に設けられている。第2導電型のソース層は、ゲート電極の他端側および該ゲート電極の下側にある半導体層内に設けられている。ゲート電極の下側においてソース層の不純物濃度は略均一である。ゲート電極およびドレイン層には同一符号の電圧が印加される。【選択図】図1
摘要翻译：要解决的问题：提供一种允许降低电源电压的隧道半导体器件。解决方案：半导体器件包括半导体层。在半导体层的表面上设置栅极绝缘膜。栅电极经由栅极绝缘膜设置在半导体层上。第一导电型漏极层设置在位于栅电极的一端侧的半导体层中。第二导电型源极层设置在位于栅极电极的另一端侧的半导体层中，位于取向电极下方。源极层的杂质浓度基本上均匀地位于栅电极下方。具有相同极性的电压施加到栅极电极和漏极层。

2. 发明专利

JP2013115113A Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2013115113A
公开(公告)日：2013-06-10
申请号：JP2011257618
申请日：2011-11-25
申请人： Toshiba Corp , 株式会社東芝
发明人： KONDO YOSHIYUKI , KAWANAKA SHIGERU
IPC分类号： H01L21/336 , H01L29/78 , H01L29/786
CPC分类号： H01L29/7391
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device capable of reducing the off-current of a tunnel FET while preventing degradation of its on-current.SOLUTION: A semiconductor device includes a substrate that has a groove, and a gate electrode that is formed at a location on the substrate adjacent to the groove via a gate insulating film and has a first side surface located on the opposite side of the groove and a second side surface located on the groove side. The device further includes a first side-wall insulating film formed on the first side surface of the gate electrode, and a second side-wall insulating film formed on the second side surface of the gate electrode and a side surface of the groove. The device further includes a first-conductivity-type source region formed, in the substrate, on the first side-wall insulating film side with respect to the first side surface of the gate electrode, and a second-conductivity-type drain region formed, in the substrate, on the second side-wall insulating film side with respect to the second side surface of the gate electrode and the side surface of the groove.
摘要翻译：要解决的问题：提供能够降低隧道FET的截止电流的同时防止其导通电流劣化的半导体器件。解决方案：半导体器件包括具有沟槽的衬底和栅电极，其经由栅极绝缘膜形成在与衬底相邻的衬底上的位置处，并且具有位于第二侧表面的相对侧上的第一侧表面所述槽和位于所述槽侧的第二侧表面。该装置还包括形成在栅电极的第一侧表面上的第一侧壁绝缘膜和形成在栅电极的第二侧表面上的第二侧壁绝缘膜和槽的侧表面。该器件还包括在衬底中形成在第一侧壁绝缘膜侧相对于栅电极的第一侧表面的第一导电型源极区域和形成的第二导电型漏极区域，在基板上，在第二侧壁绝缘膜侧相对于栅电极的第二侧面和槽的侧面。版权所有（C）2013，JPO＆INPIT

3. 发明专利

JP2010073985A Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：JP2010073985A
公开(公告)日：2010-04-02
申请号：JP2008241345
申请日：2008-09-19
申请人： Toshiba Corp , 株式会社東芝
发明人： GOTO MASAKAZU , KAWANAKA SHIGERU
IPC分类号： H01L21/8238 , H01L27/092 , H01L29/423 , H01L29/49 , H01L29/78
CPC分类号： H01L21/823828 , H01L21/823842 , H01L27/092 , H01L29/4958 , H01L29/4966 , H01L29/517 , H01L29/518 , H01L29/7833 , H01L29/7845
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device mixedly mounted with n-type and p-type MISFETs using metal gate electrodes and each set at an appropriate threshold voltage while suppressing degradation of operational characteristics.
SOLUTION: The semiconductor device includes: an n-type transistor including a first gate electrode including a first metal layer formed through a first gate insulation film on a semiconductor substrate, and a first conductive layer on the first metal layer; and a p-type transistor including a second gate electrode including a second metal layer formed through a second gate insulation film on the semiconductor substrate, having a thickness larger than that of the first metal layer, and formed of a material containing constituent elements identical to those of the first metal layer, and a second conductive layer on the second metal layer.
COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：提供一种使用金属栅电极混合安装n型和p型MISFET的半导体器件，并且每个设置在适当的阈值电压，同时抑制操作特性的降低。解决方案：半导体器件包括：n型晶体管，包括：第一栅极，其包括通过半导体衬底上的第一栅极绝缘膜形成的第一金属层和第一金属层上的第一导电层; 以及p型晶体管，其包括第二栅电极，所述第二栅极包括通过半导体衬底上的第二栅极绝缘膜形成的第二金属层，其厚度大于第一金属层的厚度，并且由含有与第一金属层的第一导电层和第二金属层上的第二导电层。版权所有（C）2010，JPO＆INPIT

4. 发明专利

JP2001267328A SEMICONDUCTOR DEVICE AND ITS MANUFACTURING METHOD 失效
公开(公告)号：JP2001267328A
公开(公告)日：2001-09-28
申请号：JP2000073411
申请日：2000-03-16
申请人： TOSHIBA CORP
发明人： YAMADA TAKASHI , KAWANAKA SHIGERU , SHINO TOMOAKI
IPC分类号： H01L21/28 , H01L21/331 , H01L21/8222 , H01L21/8248 , H01L21/8249 , H01L23/52 , H01L27/06 , H01L27/12 , H01L29/41 , H01L29/417 , H01L29/73 , H01L29/786
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device which can reduce the collector resistance of a bipolar transistor having an intrinsic emitter region, intrinsic base region and intrinsic collector region arranged in the vertical direction in a thin SOI layer of several tens to several hundreds of nanometers, and avoid deteriorating characteristics due to current concentration on the intrinsic collector region. SOLUTION: The semiconductor device (5, 6, 8, 18), provided in a semiconductor layer on an insulation film (1) through which a current flows in the thickness direction of the semiconductor layer and comprises a conductive layer (17) which adjoins the semiconductor device and is embedded in the insulation film, and an electrode (29) electrically connected to the conductive layer, and the current flows to the electrode via the interface between the semiconductor device and the conductive layer.

5. 发明专利

JP2000195869A SEMICONDUCTOR DEVICE AND ITS MANUFACTURE 失效
公开(公告)号：JP2000195869A
公开(公告)日：2000-07-14
申请号：JP36728598
申请日：1998-12-24
申请人： TOSHIBA CORP
发明人： KAWANAKA SHIGERU , YAMADA TAKASHI , ARAI HIDEAKI
IPC分类号： H01L29/73 , H01L21/331
摘要： PROBLEM TO BE SOLVED: To improve the high frequency property of a semiconductor device by equipping it with a second conductivity type of inner base lead-out region, which connects an inner base region with an outer base region, and constituting this inner base lead-out region and the inner base region of single-crystalline semiconductor films. SOLUTION: An Si oxide film 1-2 and a single-crystalline Si film 1-3 are slacked on an Si substrate 1-1, and thereon an SiO2 film 1-4, a polycrystalline Si film 1-5 as a conductive film to serve as an outer base lead-out region, and an SiO2 film 1-6 as an insulating film are stacked in this order. Then, an amorphous Si film 1-8 is stacked over the entire wafer, and the amorphous Si film 1-8 is recrystallized into a single-crystalline Si film 1-9 in a region in contact with the single-crystal Si layer 1-3 and into a polycrystalline Si film in other regions. Then, the inner base region 1-9 and the polycrystalline Si film 1-5 which serve as an outer base lead-out region are connected with each other to constitute a single-crystalline semiconductor film as an inner base lead-out region.

6. 发明专利

JPH11330083A LATERAL BIPOLAR TRANSISTOR 失效
公开(公告)号：JPH11330083A
公开(公告)日：1999-11-30
申请号：JP13799498
申请日：1998-05-20
申请人： TOSHIBA CORP
发明人： KAWANAKA SHIGERU
IPC分类号： H01L29/73 , H01L21/331
摘要： PROBLEM TO BE SOLVED: To improve high frequency characteristic of a lateral bipolar transistor. SOLUTION: This lateral bipolar transistor has an insulator layer 102; a semiconductor layer 103 formed on the insulator layer; an emitter region 104 with a first conductivity type formed on the semiconductor layer a base region 105 which is formed on the semiconductor layer, is adjacent to the emitter region 104, and has a second conductivity type; and collector region 106 which is formed in the semiconductor layer 103, is adjacent to the base region 105, and has a first conductivity type; and a base lead-out electrode region 108 which is formed in contact with the base region 105 and the collector region 106, and has a second conductivity type.

7. 发明专利

JPH11233521A MANUFACTURE OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH11233521A
公开(公告)日：1999-08-27
申请号：JP3004098
申请日：1998-02-12
申请人： TOSHIBA CORP
发明人： YOSHIMI MAKOTO , INOU KAZUMI , YAMADA TAKASHI , SHINO TOMOAKI , TERAUCHI MAMORU , KAWANAKA SHIGERU , YOSHITOMI SADAYUKI
IPC分类号： H01L29/73 , H01L21/331
摘要： PROBLEM TO BE SOLVED: To form a fine base with a high accuracy and connect the internal base with a base electrode with a low base resistance, by introducing an impurity after reducing a mask, performing heat treatment, and forming an internal base region and an external base region connected with it by self alignment. SOLUTION: At the time of removing a silicon oxide film thinly deposited on a silicon nitride film 400 by etching, a CVD mask 410 is etched at the same time, and the size is reduced from the size prior to etching, and the base silicon nitride film 400 is exposed. Boron is implanted by ion implantation to a silicon layer 20' of a portion where it is not covered with the CVD mask 410 nor a resist mask 430 through the silicon oxide film 400. An internal base region 18 is formed by heat treatment. A p-type region 26A having a high carrier concentration and a p-type region 26B having a low carrier concentration are formed by self-alignment. Thus, a fine internal base region is formed with a high dimensional accuracy.

8. 发明专利

JP2014053424A Pass gate and semiconductor memory device having the same 有权
标题翻译：通孔和半导体存储器件
公开(公告)号：JP2014053424A
公开(公告)日：2014-03-20
申请号：JP2012196366
申请日：2012-09-06
申请人： Toshiba Corp , 株式会社東芝
发明人： NAKATSUKA KEISUKE , KAWANAKA SHIGERU
IPC分类号： H01L21/8244 , H01L21/336 , H01L21/8234 , H01L27/08 , H01L27/088 , H01L27/11 , H01L29/78 , H01L29/786
CPC分类号： H01L27/088 , G11C11/412 , H01L27/0207 , H01L27/1104 , H01L29/7391
摘要： PROBLEM TO BE SOLVED: To provide a pass gate using tunnel transistors that allows improving cut-off characteristics, and a semiconductor memory device having the same.SOLUTION: A semiconductor memory device includes an SRAM cell. The SRAM cell has first and second transfer gates each constituted by a pass gate. The pass gate has first and second tunnel transistors. The first tunnel transistor has a first diffusion region of a first conductivity type as a source region or a drain region, a second diffusion region of a second conductivity type as the drain region or the source region, and a gate electrode receiving a control voltage. The second tunnel transistor has a first diffusion region of the first conductivity type as a source region or a drain region, a second diffusion region of the second conductivity type as the drain region or the source region connected to the second diffusion region of the first tunnel transistor, and a gate electrode connected to the gate electrode of the first tunnel transistor.
摘要翻译：要解决的问题：提供一种使用允许提高截止特性的隧道晶体管的栅极，以及具有该栅极特性的半导体存储器件。解决方案：半导体存储器件包括SRAM单元。 SRAM单元具有由传递门构成的第一和第二传输门。传输门具有第一和第二隧道晶体管。第一隧道晶体管具有第一导电类型的第一扩散区域作为源极区域或漏极区域，第二导电类型的第二扩散区域作为漏极区域或源极区域，以及栅极电极接收控制电压。第二隧道晶体管具有第一导电类型的第一扩散区域作为源极区域或漏极区域，作为漏极区域的第二导电类型的第二扩散区域或连接到第一隧道的第二扩散区域的源极区域晶体管和连接到第一隧道晶体管的栅电极的栅电极。

9. 发明专利

JP2012059946A Manufacturing method of semiconductor device 审中-公开
标题翻译：半导体器件的制造方法
公开(公告)号：JP2012059946A
公开(公告)日：2012-03-22
申请号：JP2010202109
申请日：2010-09-09
申请人： Toshiba Corp , 株式会社東芝
发明人： KONDO YOSHIYUKI , OKANO OUSHIYUN , KAWANAKA SHIGERU
IPC分类号： H01L27/088 , H01L21/8234 , H01L21/8242 , H01L27/108 , H01L29/78
CPC分类号： H01L21/823412 , H01L21/2652 , H01L21/26586 , H01L21/823425 , H01L21/823437 , H01L29/1083 , H01L29/66545
摘要： PROBLEM TO BE SOLVED: To provide a manufacturing method of a semiconductor device capable of forming a halo region having an appropriate concentration profile on a transistor in which a cap film on a gate electrode is thick and a space ratio aspect between adjacent transistors is large.SOLUTION: A manufacturing method of a semiconductor device according to an embodiment includes: a step of forming a first gate electrode and a second gate electrode on a substrate; a step of forming a first halo region under the first gate electrode and a second halo region under the second gate electrode; and a step of forming a first cap film whose bottom face and side face are covered by a first insulating film and a second cap film whose bottom face and side face are covered by a second insulating film. The first halo region is formed by driving a first impurity into the substrate through the second insulating film. The second halo region is formed by driving a second impurity into the substrate through the first insulating film.
摘要翻译：解决的问题：提供一种半导体器件的制造方法，该半导体器件能够在晶体管上形成具有适当浓度分布的卤素区域，其中栅电极上的帽膜厚，并且相邻晶体管之间的空间比方面很大解决方案：根据实施例的半导体器件的制造方法包括：在衬底上形成第一栅电极和第二栅电极的步骤; 在所述第一栅电极下方形成第一晕区和在所述第二栅电极下方的第二晕区的步骤; 以及形成其底面和侧面被第一绝缘膜覆盖的第一盖膜和底面和侧面被第二绝缘膜覆盖的第二盖膜的步骤。通过第二绝缘膜将第一杂质驱动到衬底中形成第一晕圈。通过第一绝缘膜将第二杂质驱动到衬底中形成第二卤区。版权所有（C）2012，JPO＆INPIT

10. 发明专利

JP2011198938A Transistor 审中-公开
标题翻译：晶体管
公开(公告)号：JP2011198938A
公开(公告)日：2011-10-06
申请号：JP2010062855
申请日：2010-03-18
申请人： Toshiba Corp , 株式会社東芝
发明人： KAWANAKA SHIGERU , TOMIYE KANNA , TSUJII HIDEJI , MIYATA TOSHITAKA
IPC分类号： H01L29/786 , H01L51/05 , H01L51/30
CPC分类号： H01L29/78684 , B82Y10/00 , H01L29/1606 , H01L29/41733 , H01L29/41775 , H01L29/45 , H01L29/778 , H01L29/7839
摘要： PROBLEM TO BE SOLVED: To provide a transistor having high current drive force and high cut-off characteristics.SOLUTION: The transistor in one embodiment includes: a graphene film 10 which is formed under a gate electrode 12 through a gate insulating film and provided with a conductor region 10a including a source side end 10S and a conductor region 10b including a drain side end 10D, and for which a width La in a channel width direction in the source side end 10S is narrower than a width Lb in the channel width direction in the drain side end 10D; a source electrode connected to the source side end 10S of the graphene film 10 to form a Schottky barrier contact; and a drain electrode connected to the drain side end 10D of the graphene film 10 to form an ohmic contact.
摘要翻译：要解决的问题：提供具有高电流驱动力和高截止特性的晶体管。解决方案：一个实施例中的晶体管包括：石墨烯膜10，其通过栅极绝缘膜形成在栅电极12下方并且具有包括源极侧端部10S的导体区域10a和包括漏极侧端部10D的导体区域10b，并且源极侧端部10S中的沟道宽度方向上的宽度La比沟道宽度方向上的宽度Lb窄在漏极侧端部10D; 源电极，其连接到石墨烯膜10的源极侧端部10S，以形成肖特基势垒接触; 以及与石墨烯薄膜10的漏极侧端部10D连接以形成欧姆接触的漏电极。

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