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1. 发明专利

JP2011159848A Solid-state imaging device and method for manufacturing the same 审中-公开
标题翻译：固态成像装置及其制造方法
公开(公告)号：JP2011159848A
公开(公告)日：2011-08-18
申请号：JP2010020999
申请日：2010-02-02
申请人： Toshiba Corp , 株式会社東芝
发明人： ARAYASHIKI YUSUKE , NAKAJIMA KAZUAKI
IPC分类号： H01L27/14 , H01L27/146
CPC分类号： H01L27/14629 , H01L27/1462 , H01L27/14621 , H01L27/14623 , H01L27/14627 , H01L27/1463 , H01L27/1464 , H01L27/14645 , H01L27/14685
摘要： PROBLEM TO BE SOLVED: To provide a solid-state imaging device, capable of forming a low-refractive-index and dark-current-annihilating layer at a relatively low temperature, and to provide a method of manufacturing the same.
SOLUTION: The solid-state imaging device 1 includes a semiconductor substrate 2 with a light receiver 20 for photoelectric converting incident light formed, a ferroelectric layer 6 made of, for example, a vinylidene fluoride compound as an organic compound formed on a surface upon which the incident light of the light receiver 20 is incident at ≤200°C, and a transparent electrode 7 formed on the ferroelectric layer 6. The ferroelectric layer 6 develops a ferroelectric by applying a voltage which is negative to the transparent electrode 7 side and is positive to the semiconductor substrate 2 side.
COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：解决的问题：提供能够在较低温度下形成低折射率和暗电流消除层的固态成像装置，并提供其制造方法。解决方案：固体摄像装置1包括具有用于光电转换入射光的光接收器20的半导体衬底2，例如由形成在其上的有机化合物的偏二氟乙烯化合物制成的铁电层6 光接收器20的入射光入射到≤200℃的表面和形成在铁电层6上的透明电极7.铁电层6通过向透明电极7施加负电压来显影铁电体并且对半导体衬底2侧是正的。版权所有（C）2011，JPO＆INPIT

2. 发明专利

JP2007207994A Semiconductor device manufacturing method 审中-公开
标题翻译：半导体器件制造方法
公开(公告)号：JP2007207994A
公开(公告)日：2007-08-16
申请号：JP2006024888
申请日：2006-02-01
申请人： Toshiba Corp , 株式会社東芝
发明人： NAKAJIMA KAZUAKI
IPC分类号： H01L29/78 , H01L21/28 , H01L21/768 , H01L21/8238 , H01L27/092 , H01L29/423 , H01L29/49
CPC分类号： H01L21/823857 , H01L21/823842 , H01L29/4966 , H01L29/517 , H01L29/665
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device manufacturing method for forming a high-quality semiconductor device by restraining variations in threshold of a p-type MOSFET while restraining costs for product development.
SOLUTION: The semiconductor device manufacturing method is provided with a first step for forming a gate insulating film 102 on a silicon substrate 100, a second step for forming a conductor film 103 constituting a gate electrode 104 on the gate insulating film 102 by a formation method using an organic material, and a third step for heating the silicon substrate 100 having the conductor film 103 in a mixed atmosphere of water vapor being an oxidizing atmosphere and hydrogen being a reduction atmosphere. A hydrogen partial-pressure ratio to water vapor in the third step is a partial pressure in which carbon is oxidized and a metal material constituting the conductor film 104 is reduced.
COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供一种通过抑制p型MOSFET的阈值变化来形成高质量半导体器件的半导体器件制造方法，同时抑制产品开发的成本。解决方案：半导体器件制造方法具有在硅衬底100上形成栅极绝缘膜102的第一步骤，用于在栅极绝缘膜102上形成构成栅极电极104的导体膜103的第二步骤，通过使用有机材料的形成方法，以及第三步骤，在作为氧化气氛的水蒸气的混合气氛中加热具有导体膜103的硅衬底100，并且将氢作为还原气氛。在第三步骤中与水蒸汽的氢分压比是碳被氧化并且构成导体膜104的金属材料减少的分压。版权所有（C）2007，JPO＆INPIT

3. 发明专利

JP2007095872A Method of manufacturing semiconductor device 审中-公开
标题翻译：制造半导体器件的方法
公开(公告)号：JP2007095872A
公开(公告)日：2007-04-12
申请号：JP2005281340
申请日：2005-09-28
申请人： Toshiba Corp , 株式会社東芝
发明人： NAKAJIMA KAZUAKI
IPC分类号： H01L29/78 , H01L21/28 , H01L21/336 , H01L21/8238 , H01L27/092 , H01L29/423 , H01L29/49
CPC分类号： H01L21/823835 , H01L21/28097 , H01L21/823871 , H01L29/66507 , H01L29/66545
摘要： PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor device including an MIS type transistor having a gate electrode consisting of metal silicide, and a source-drain region having a deep diffusion layer and a shallow diffusion layer.
SOLUTION: The gate electrode comprises a gate insulating film, a first gate electrode film, a first insulating film, and a second gate electrode film. The ion implantation is carried out so as to form a first diffusion layer by using as a mask the gate electrode and a first side wall formed at the side of the gate electrode. A second side wall 13 is formed in the side of the gate electrode after removing the first side wall, and the ion implantation is carried out by using as a mask the gate electrode and the second side wall so as to form a second diffusion layer. A first metal film is formed on the second gate electrode film and is made to react so that the second gate electrode film may be a first reaction layer. The first reaction layer on the gate electrode is removed, and after forming an interlayer dielectric 21, it is made flat until the upper surface of the first gate electrode film of the gate electrode is exposed. A second reaction layer 6a has a portion wherein the second metal film is formed, it is made to react with the first gate electrode film, and the first gate electrode film is brought into contact with the gate insulatiing film.
COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供一种制造半导体器件的方法，该半导体器件包括具有由金属硅化物构成的栅极的MIS型晶体管和具有深扩散层和浅扩散层的源极 - 漏极区域。解决方案：栅极包括栅极绝缘膜，第一栅极电极膜，第一绝缘膜和第二栅极电极膜。进行离子注入，以便通过使用栅电极和形成在栅极侧的第一侧壁作为掩模形成第一扩散层。在除去第一侧壁之后，在栅电极的侧面形成第二侧壁13，并且通过使用栅电极和第二侧壁作为掩模来进行离子注入，以形成第二扩散层。在第二栅极电极膜上形成第一金属膜，使第二栅极电极膜成为第一反应层。除去栅电极上的第一反应层，在形成层间电介质21之后，使其平坦，直到栅电极的第一栅电极膜的上表面露出。第二反应层6a具有形成第二金属膜的部分，使其与第一栅电极膜反应，并使第一栅电极膜与栅极绝缘膜接触。版权所有（C）2007，JPO＆INPIT

4. 发明专利

JP2006287134A Semiconductor device and its manufacturing method 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2006287134A
公开(公告)日：2006-10-19
申请号：JP2005107937
申请日：2005-04-04
申请人： Toshiba Corp , 株式会社東芝
发明人： NAKAJIMA KAZUAKI , SUGURO KYOICHI
IPC分类号： H01L27/092 , H01L21/28 , H01L21/768 , H01L21/8238 , H01L29/417 , H01L29/423 , H01L29/49
CPC分类号： H01L21/823842 , H01L21/28079 , H01L29/4958 , H01L29/66545 , H01L29/6656 , H01L29/6659 , H01L29/7833 , Y10S438/976
摘要： PROBLEM TO BE SOLVED: To form a metal gate electrode having a work function which is different between a p-type MOSFET and an n-type MOSFET without greatly increasing the number of manufacturing stages.
SOLUTION: A semiconductor device has an n-type MOS transistor and a p-type MOS transistor. A gate electrode 107n of the n-type MOS transistor has a tungsten film 105n contacting a gate insulating film 104, a gate electrode 107p of the p-type MOS transistor has a tungsten film 105p contacting the gate insulating film 104, and the density of carbon contained in the tungsten film 105n is lower than the density of carbon contained in the tungsten film 105p.
COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：为了形成具有p型MOSFET和n型MOSFET不同的功函数的金属栅电极，而不会大大增加制造阶段的数量。解决方案：半导体器件具有n型MOS晶体管和p型MOS晶体管。 n型MOS晶体管的栅电极107n具有与栅极绝缘膜104接触的钨膜105n，p型MOS晶体管的栅电极107p具有与栅极绝缘膜104接触的钨膜105p，包含在钨膜105n中的碳比在钨膜105p中包含的碳的密度低。版权所有（C）2007，JPO＆INPIT

5. 发明专利

JP2005340336A Semiconductor device and its manufacturing method 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2005340336A
公开(公告)日：2005-12-08
申请号：JP2004154406
申请日：2004-05-25
申请人： Toshiba Corp , 株式会社東芝
发明人： NAKAJIMA KAZUAKI
IPC分类号： H01L21/28 , H01L21/336 , H01L21/768 , H01L21/8234 , H01L21/8238 , H01L27/088 , H01L27/12 , H01L29/49 , H01L29/78
CPC分类号： H01L21/823835 , H01L21/823842 , H01L21/823857 , H01L29/4933 , H01L29/665 , H01L29/7843
摘要： PROBLEM TO BE SOLVED: To open a contact above a silicided gate electrode and a diffusion layer without damaging the gate electrode and the diffusion layer.
SOLUTION: The semiconductor device comprises the gate electrode 111 formed of a metal silicide on a silicon substrate 100, the diffusion layer 107 which is so formed as to be located on both sides of a channel region on the surface of the silicon substrate 100 and which has a silicide film 108 formed on the surface thereof, insulation films 109 and 114 formed on top of the silicide film 108 of the diffusion layer 107, and an insulation film 114 formed on the gate electrode 111. The insulation films 109 and 114 on the diffusion layer 108 are formed thicker than the insulation film 114 on the gate electrode 111.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：打开硅化物栅电极和扩散层之上的接触，而不损坏栅电极和扩散层。解决方案：半导体器件包括在硅衬底100上由金属硅化物形成的栅电极111，其形成为位于硅衬底表面上的沟道区两侧的扩散层107 100，其表面上形成有硅化物膜108，形成在扩散层107的硅化物膜108的顶部上的绝缘膜109和114以及形成在栅电极111上的绝缘膜114.绝缘膜109和 114形成在扩散层108上比栅电极111上的绝缘膜114厚。版权所有（C）2006，JPO＆NCIPI

6. 发明专利

JP2004087877A Field effect semiconductor device and method for manufacturing the same 审中-公开
标题翻译：场效应半导体器件及其制造方法
公开(公告)号：JP2004087877A
公开(公告)日：2004-03-18
申请号：JP2002248079
申请日：2002-08-28
申请人： Fujitsu Ltd , Toshiba Corp , 富士通株式会社 , 株式会社東芝
发明人： SUGIZAKI TARO , AKASAKA YASUSHI , NAKAJIMA KAZUAKI
IPC分类号： H01L29/423 , H01L21/8242 , H01L27/108 , H01L29/49 , H01L29/78
摘要： PROBLEM TO BE SOLVED: To provide a gate electrode having a high melting metal structure of Si/WSi/WN, low in contact resistance and high in thermal stability. SOLUTION: In the manufacturing of this field effect semiconductor device, it is so set that a mathematical expression d WSi ≤(1.25d WN ) 1/2 be satisfied, wherein d WSi [nm] is the thickness of a WSi layer 6 which is a constituent of a gate electrode 4 having a high melting metal structure of Si/WSi/WN and d WN [nm] is the thickness of a WN layer 7 which is another constituent located farther from a gate insulating film 2 than the WSi layer 6 is. COPYRIGHT: (C)2004,JPO
摘要翻译：要解决的问题：提供具有高熔点金属结构的Si / WSi / WN的栅电极，接触电阻低和热稳定性高。解决方案：在该场效应半导体器件的制造中，将数学表达式设定为数学表达式，其中，数学表达式为：SP1 =（1.25d WN ） 1 / 2 ，其中d WSi [nm]是WSi层6的厚度，WSi层6是具有Si / WSi / WN的高熔融金属结构的栅电极4的组成并且d W N [nm]是与WSi层6相比位于比栅极绝缘膜2更远的另一个成分的WN层7的厚度。版权所有（C）2004，JPO

7. 发明专利

JP2014170789A Semiconductor device, and method of manufacturing the same 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2014170789A
公开(公告)日：2014-09-18
申请号：JP2013040655
申请日：2013-03-01
申请人： Toshiba Corp , 株式会社東芝
发明人： ITO YOSHINOBU , KATO ATSUSHI , OMOTO SEIICHI , NAKAJIMA KAZUAKI , TOYODA HIROSHI
IPC分类号： H01L27/115 , H01L21/3065 , H01L21/3205 , H01L21/336 , H01L21/768 , H01L21/8247 , H01L27/10 , H01L29/788 , H01L29/792
摘要： PROBLEM TO BE SOLVED: To thin a wiring pattern while reducing the number of steps in a side wall processing process.SOLUTION: A side wall pattern 6A consisting of a conductor is formed on a side wall of a core material pattern 3A. The core material pattern 3A is removed while remaining the side wall pattern 6A on a seed layer 2. The seed layer 2 is etched via the side wall pattern 6A. Thereby, a wire consisting of the side wall pattern 6A and the seed layer 2 is formed on a base layer 1.
摘要翻译：要解决的问题：减少侧壁加工工艺中的步骤数量，减少布线图案。解决方案：在芯材图案3A的侧壁上形成由导体构成的侧壁图案6A。芯材料图案3A被去除，同时保留在种子层2上的侧壁图案6A。籽晶层2经由侧壁图案6A被蚀刻。由此，在基底层1上形成由侧壁图案6A和种子层2构成的线。

8. 发明专利

JP2010073865A Semiconductor device, and method for manufacturing the same 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2010073865A
公开(公告)日：2010-04-02
申请号：JP2008239200
申请日：2008-09-18
申请人： Toshiba Corp , 株式会社東芝
发明人： IKENO DAISUKE , AOYAMA TOMONORI , NAKAJIMA KAZUAKI , INUMIYA SEIJI , SHIMIZU TAKASHI , KOBAYASHI TAKUYA
IPC分类号： H01L21/8238 , H01L21/28 , H01L27/092 , H01L29/423 , H01L29/49 , H01L29/78
CPC分类号： H01L21/823807 , H01L21/823828
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device and a method for manufacturing the same wherein an effective work function of a gate electrode can be stably set at a value near mid-gap of an Si band gap, in the semiconductor device having an NMOS and a PMOS such as an NMOSFET and a PMOSFET.
SOLUTION: The semiconductor device is configured by including: a semiconductor substrate which has a p-type diffusion layer and an n-type diffusion layer separated by an element isolating means; a gate insulating film formed on each of the p-type diffusion layer and the n-type diffusion layer of the semiconductor substrate; the gate electrode containing a metal film formed on the gate insulating film; a Ge inclusion formed at an interface between the gate insulating film and the metal film; and a silicon-contained layer formed on the metal film.
COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：为了提供半导体器件及其制造方法，其中在半导体器件中可以将栅电极的有效功函数稳定地设定在接近中间间隙的值具有NMOS和诸如NMOSFET和PMOSFET的PMOS。解决方案：半导体器件通过包括：半导体衬底，其具有由元件隔离装置隔开的p型扩散层和n型扩散层; 形成在半导体衬底的p型扩散层和n型扩散层中的每一个上的栅极绝缘膜; 所述栅极电极含有形成在所述栅极绝缘膜上的金属膜; 形成在栅极绝缘膜和金属膜之间的界面处的Ge夹杂物; 以及形成在金属膜上的含硅层。版权所有（C）2010，JPO＆INPIT

9. 发明专利

JP2009267118A Method for manufacturing semiconductor device, and semiconductor device 审中-公开
标题翻译：制造半导体器件的方法和半导体器件
公开(公告)号：JP2009267118A
公开(公告)日：2009-11-12
申请号：JP2008115594
申请日：2008-04-25
申请人： Toshiba Corp , 株式会社東芝
发明人： NAKAJIMA KAZUAKI
IPC分类号： H01L29/78 , H01L21/283 , H01L21/8238 , H01L27/092 , H01L29/423 , H01L29/49
CPC分类号： H01L21/28194 , H01L21/28088 , H01L21/28176 , H01L21/823807 , H01L21/823842 , H01L21/823857 , H01L29/4966 , H01L29/513 , H01L29/517 , H01L29/6659 , H01L29/7833
摘要： PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor device and a semiconductor device, wherein the reliability of a gate insulating film and the performance of the semiconductor device can be secured.
SOLUTION: In the method for manufacturing a semiconductor device, a gate insulating film formation process for forming a gate insulating film 103 on an Si substrate 100, a first metal film formation process for forming a first metal film on the gate insulating film 103, a second metal film formation process for forming a second metal film composing a metal electrode 104 on the first metal film, and a reaction film formation process for forming a reaction film 118 reacting to the gate insulating film 103 and the first metal film between the gate insulating film 103 and the first metal film by heat treating are performed to recover damage of the gate insulating film 103, which may be generated in the first metal film formation process.
COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：提供一种半导体器件和半导体器件的制造方法，其中可以确保栅极绝缘膜的可靠性和半导体器件的性能。解决方案：在半导体器件的制造方法中，在Si衬底100上形成栅极绝缘膜103的栅极绝缘膜形成工艺，用于在栅极绝缘膜上形成第一金属膜的第一金属膜形成工艺 103是在第一金属膜上形成构成金属电极104的第二金属膜的第二金属膜形成工艺，以及用于形成反应膜118的反应膜形成工序，该反应膜118与栅极绝缘膜103和第一金属膜之间形成反应膜118，进行栅极绝缘膜103和通过热处理的第一金属膜，以恢复在第一金属膜形成工艺中可能产生的栅极绝缘膜103的损伤。版权所有（C）2010，JPO＆INPIT

10. 发明专利

JP2008282856A Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：JP2008282856A
公开(公告)日：2008-11-20
申请号：JP2007123362
申请日：2007-05-08
申请人： Toshiba Corp , 株式会社東芝
发明人： NAKAJIMA KAZUAKI
IPC分类号： H01L21/8238 , H01L27/092 , H01L29/423 , H01L29/49 , H01L29/78
CPC分类号： H01L21/823842 , H01L21/28079 , H01L21/823871 , H01L29/4958
摘要： PROBLEM TO BE SOLVED: To prevent the operating speed from falling by reducing interface resistance on the polysilicon/metal interface of a polysilicon/metal laminated electrode structure. SOLUTION: The semiconductor device comprises an n-channel MISFET having a semiconductor substrate 100, a diffusion layer 103 formed in region N1 to sandwich a channel region 102, a gate insulating film 104, and a gate electrode 105 including metal films 105a, 105b and an n-type polysilicon film 105c, and a p-channel MISFET having a diffusion layer 203 formed in region P1 to sandwich a channel region 202 and containing boron as dopant, a gate insulating film 204, and a gate electrode 205 including metal films 205a-c and a metal film 205c containing nitrogen and an n-type polysilicon film 205d having the boron concentration of 5E19 cm -3 or less at the interface. COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：通过降低多晶硅/金属层叠电极结构的多晶硅/金属界面上的界面电阻来防止工作速度下降。解决方案：半导体器件包括具有半导体衬底100的n沟道MISFET，在区域N1中形成以夹持沟道区102的扩散层103，栅极绝缘膜104和包括金属膜105a的栅电极105 ，105b和n型多晶硅膜105c以及在区域P1中形成有扩散层203以夹持沟道区202并含有硼作为掺杂剂的p沟道MISFET，栅极绝缘膜204和栅极电极205，包括金属膜205a-c和含有氮的金属膜205c和界面处硼浓度为5E19cm 3以上的n型多晶硅膜205d。版权所有（C）2009，JPO＆INPIT

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