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    • 111. 发明专利
    • Semiconductor device and manufacturing method thereof
    • 半导体器件及其制造方法
    • JP2005033030A
    • 2005-02-03
    • JP2003271353
    • 2003-07-07
    • Matsushita Electric Ind Co Ltd松下電器産業株式会社
    • KUSUMOTO OSAMUKITAHATA MAKOTOUCHIDA MASAOTAKAHASHI KUNIMASAYAMASHITA MASAYAMIYANAGA RYOKO
    • H01L21/28H01L29/12H01L29/417H01L29/78
    • PROBLEM TO BE SOLVED: To provide a semiconductor device for preventing the occurrence of a broken electrode, local increase in the electric resistance, and electromigration or the like, and to provide a manufacturing method thereof. SOLUTION: The manufacturing method sequentially forms a high resistance SiC layer 2 and a p-well region 3, carries out epitaxial growing of a channel layer 5 and thereafter, forms a p+ contact region 4 to part of the channel layer 5 and the p-well region 3, forms a source region 6 surrounding sides of the p+ contact region 4 by using an implantation mask open to the upper part of the p+ contact region 4, and thereafter forms a source electrode 8 bridged over the source region 6 and the p+ contact region 4. Since there exists almost no step difference at the base of the source electrode 8, the occurrence of the electromigration of, the break in and the local increase in the electric resistance of the source electrode 8 is suppressed. COPYRIGHT: (C)2005,JPO&NCIPI
    • 要解决的问题:提供一种用于防止电极断裂发生的半导体器件,电阻的局部增加和电迁移等,并提供其制造方法。 解决方案:制造方法依次形成高电阻SiC层2和p阱区域3,进行沟道层5的外延生长,此后,形成沟道层5的一部分的p +接触区域4,以及 p阱区域3通过使用向p +接触区域4的上部开放的注入掩模形成围绕p +接触区域4的侧面的源极区域6,然后形成桥接在源极区域6上的源极电极8 和p +接触区域4.由于在源电极8的基部几乎没有阶梯差,所以抑制了电极的电迁移,电源电极8的电阻的局部增加的发生。 版权所有(C)2005,JPO&NCIPI
    • 112. 发明专利
    • Method for manufacturing semiconductor device
    • 制造半导体器件的方法
    • JP2004014709A
    • 2004-01-15
    • JP2002164631
    • 2002-06-05
    • Matsushita Electric Ind Co Ltd松下電器産業株式会社
    • UCHIDA MASAOKITAHATA MAKOTOMIYANAGA RYOKOTAKAHASHI KUNIMASAKUSUMOTO OSAMUYAMASHITA MASAYA
    • H01L21/28H01L21/301H01L21/336H01L29/12H01L29/41H01L29/78
    • PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor device capable of reducing the occurrence of a defective element due to the breakage or chipping off of a crystal in chip separation. SOLUTION: On a wafer 11 comprising a silicon carbide substrate and a silicon carbide layer, an upper electrode 6 is arranged side by side nearly along a direction Y which is one of cleavage directions and a direction X which is tilted from the cleavage direction by at least 5°. Then, when separating an element formed on the wafer 11 into a plurality of chips 10, the chip is cut off along a separation line 14a which is nearly parallel to the cleavage direction Y and a separation line 14b which is nearly parallel to the direction X. In this case, arranging of the electrode 6 side by side and chip separation are performed with a step formed on the silicon carbide as reference, thereby the cleavage direction is known precisely to reduce occurrence of the breakage or chipping off in the semiconductor chip in chip separation. COPYRIGHT: (C)2004,JPO
    • 解决问题的方案:提供一种半导体器件的制造方法,该半导体器件能够减少由于芯片分离中的晶体的断裂或破裂而导致的缺陷元件的发生。 解决方案:在包括碳化硅衬底和碳化硅层的晶片11上,上电极6大致沿着作为解理方向之一的方向Y和从切割方向倾斜的方向X并排布置 方向至少5°。 然后,当将形成在晶片11上的元件分成多个芯片10时,沿着与解理方向Y几乎平行的分离线14a切割芯片,并且分离线14b几乎平行于X方向 在这种情况下,以碳化硅为基准的台阶形成并列排列电极6和芯片分离,精确地知道切割方向,以减少半导体芯片中的断裂或破裂的发生 芯片分离。 版权所有(C)2004,JPO