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1. 发明专利

JP2007053227A Semiconductor device and its manufacturing method 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2007053227A
公开(公告)日：2007-03-01
申请号：JP2005237183
申请日：2005-08-18
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： YAMASHITA MASAYA , KITAHATA MAKOTO , KUSUMOTO OSAMU , TAKAHASHI KUNIMASA , UCHIDA MASAO
IPC分类号： H01L21/316 , H01L21/322 , H01L21/336 , H01L21/822 , H01L27/04 , H01L29/12 , H01L29/78
摘要： PROBLEM TO BE SOLVED: To form an oxide layer with low metal impurity concentration on the surface of a semiconductor layer employing a chemically stable semiconductor such as silicon carbide.
SOLUTION: The manufacturing method of a semiconductor element comprises a process (A) of cleaning the surface of the semiconductor layer 12 consisting of a wide band gap semiconductor using gas containing a halogen group element, and a process (B) of forming an oxide layer 14 on the surface of the semiconductor layer 12.
COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：使用化学稳定的半导体如碳化硅在半导体层的表面上形成具有低金属杂质浓度的氧化物层。解决方案：半导体元件的制造方法包括：使用含有卤素族元素的气体的宽带隙半导体构成的半导体层12的表面的清洗工序（A）和形成半导体层12的表面上的氧化物层14.（C）2007，JPO＆INPIT

2. 发明专利

JP2006049402A Inverter device 审中-公开
标题翻译：逆变器装置
公开(公告)号：JP2006049402A
公开(公告)日：2006-02-16
申请号：JP2004225102
申请日：2004-08-02
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： TAKAHASHI KUNIMASA , KITAHATA MAKOTO , KUSUMOTO OSAMU , UCHIDA MASAO , YAMASHITA MASAYA , MIYANAGA RYOKO , HASHIMOTO KOICHI
IPC分类号： H01L21/8234 , H01L21/8238 , H01L27/08 , H01L27/088 , H01L27/092 , H02M1/00 , H02M7/5387
CPC分类号： Y02B70/1483
摘要： PROBLEM TO BE SOLVED: To provide a small and super-low loss silicon carbide semiconductor inverter device which can operate even in high temperature environment. SOLUTION: A first lateral MOSFET 1 and a second lateral MOSFET 2 of a power device are formed on a common silicon carbide substrate 100 while being isolated electrically by an element isolation region 18. Drain electrode 16 of the first lateral MOSFET 1 is connected electrically with source electrode 15 of the second lateral MOSFET 2 on the silicon carbide substrate 100. Elements constituting the control circuit 21 of the lateral MOSFETs 1 and 2 are also formed on the same silicon carbide substrate 100 while being isolated electrically from the lateral MOSFETs 1 and 2 by an element isolation region 22. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供即使在高温环境下也能够工作的小型超低损耗碳化硅半导体逆变器装置。解决方案：功率器件的第一横向MOSFET 1和第二横向MOSFET 2形成在公共碳化硅衬底100上，同时被元件隔离区18电隔离。第一横向MOSFET 1的漏极电极16 与碳化硅衬底100上的第二横向MOSFET 2的源电极15电连接。构成横向MOSFET 1和2的控制电路21的元件也形成在同一碳化硅衬底100上，同时与横向MOSFET隔离元件隔离区域22。（C）2006，JPO＆NCIPI

3. 发明专利

JP2005353877A Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：JP2005353877A
公开(公告)日：2005-12-22
申请号：JP2004173716
申请日：2004-06-11
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： HASHIMOTO KOICHI , KITAHATA MAKOTO , KUSUMOTO OSAMU , UCHIDA MASAO , TAKAHASHI KUNIMASA , MIYANAGA RYOKO , YAMASHITA MASAYA , IWANAGA JUNKO
IPC分类号： H01L29/78 , H01L21/336 , H01L29/12 , H01L29/739
摘要： PROBLEM TO BE SOLVED: To provide a normally-off vertical power MOSFET where on-resistance equivalent to a conduction loss can be reduced.
SOLUTION: A semiconductor device 100 is provided with a semiconductor layer 2 consisting of a first semiconductor; second conductive well areas 6 which are formed at the semiconductor layer 2 so as to include the surface of the semiconductor 2; a first conductive conduction area 2a formed in the semiconductor layer 2 extending the whole thickness of the semiconductor layer 2 in contact with the well areas 6; a channel layer 3 formed on at least a part of the well areas 6 and at least a part of the conduction area 2a, and consisting of a semiconductor; and a gate electrode 12 formed on the channel layer 3. At least a part of the channel layer 3 positioned under the gate electrode 12 consists of a second semiconductor, and the band gap of the first semiconductor is larger than that of the second semiconductor.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供一种常闭垂直功率MOSFET，其中导通电阻等于导通损耗可以降低。解决方案：半导体器件100设置有由第一半导体构成的半导体层2; 第二导电阱区域6，其形成在半导体层2上以包括半导体2的表面; 形成在半导体层2中的第一导电导电区域2a延伸与阱区域6接触的半导体层2的整个厚度; 形成在阱区域6的至少一部分和导电区域2a的至少一部分上并由半导体构成的沟道层3; 以及形成在沟道层3上的栅电极12.位于栅电极12下方的沟道层3的至少一部分由第二半导体构成，第一半导体的带隙大于第二半导体的带隙。版权所有（C）2006，JPO＆NCIPI

4. 发明专利

JP2005343744A Method for producing carbon nanotube semiconductor and carbon nanotube semiconductor 审中-公开
标题翻译：生产碳纳米管半导体和碳纳米管半导体的方法
公开(公告)号：JP2005343744A
公开(公告)日：2005-12-15
申请号：JP2004165311
申请日：2004-06-03
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： TAKAHASHI KUNIMASA , KITAHATA MAKOTO , KUSUMOTO OSAMU , UCHIDA MASAO , YAMASHITA MASAYA , MIYANAGA RYOKO , HASHIMOTO KOICHI
IPC分类号： B82B3/00 , C01B31/02 , C23C16/42 , H01L21/205 , H01L21/265 , H01L29/06
摘要： PROBLEM TO BE SOLVED: To more exactly control the conductivity of a carbon nanotube semiconductor. SOLUTION: The method for producing the carbon nanotube semiconductor includes (A) a process for preparing a silicon carbide layer 2 doped with an impurity governing the conductivity type, and (B) a process for forming the carbon nanotube semiconductor 5 by graphitizing a portion or the whole of the silicon carbide layer 2. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：更准确地控制碳纳米管半导体的导电性。解决方案：用于制造碳纳米管半导体的方法包括（A）制备掺杂有导电类型的杂质的碳化硅层2的工艺，（B）通过石墨化形成碳纳米管半导体5的工艺碳化硅层2的一部分或全部。版权所有（C）2006，JPO＆NCIPI

5. 发明专利

JP2005229105A Semiconductor element and its manufacturing method 审中-公开
标题翻译：半导体元件及其制造方法
公开(公告)号：JP2005229105A
公开(公告)日：2005-08-25
申请号：JP2005005750
申请日：2005-01-12
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： UCHIDA MASAO , KITAHATA MAKOTO , KUSUMOTO OSAMU , YAMASHITA MASAYA , TAKAHASHI KUNIMASA , MIYANAGA RYOKO , HASHIMOTO KOICHI , OSADA KAORU
IPC分类号： H01L21/3065 , H01L21/265 , H01L21/336 , H01L29/12 , H01L29/78
摘要： PROBLEM TO BE SOLVED: To enable a step to be produced in an interface between an impurity implantation region and an impurity non-implantation region to be smaller, when forming an impurity implantation mask on a semiconductor layer.
SOLUTION: The protection layer 25 of an oxide film, a first aluminum layer 26, and a second oxide film 27 are formed as a mask for impurity injection on a silicon carbide layer 12. Then, the second film 27 is patterned by performing dry etching. At that time, the first film 26 becomes an etching stopper and the etching stops on the first film 26. Then, after a portion exposed in the first film 26 is removed, by etching, the impurity injection is carried out from above the protective layer 25 into a silicon carbide layer 12; and the remaining protective layer 25, the first film 26, and the second film 27 are removed.
COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：为了使在半导体层上形成杂质注入掩模时在杂质注入区域和杂质非注入区域之间的界面中产生的步骤更小。解决方案：在碳化硅层12上形成氧化膜，第一铝层26和第二氧化物膜27的保护层25作为用于杂质注入的掩模。然后，第二膜27被图案化进行干蚀刻。此时，第一膜26成为蚀刻停止剂，并且蚀刻停止在第一膜26上。然后，在去除在第一膜26中暴露的部分之后，通过蚀刻，从保护层的上方进行杂质注入 25成为碳化硅层12; 并且除去剩余的保护层25，第一膜26和第二膜27。版权所有（C）2005，JPO＆NCIPI

6. 发明专利

JP2004253427A Silicon carbide semiconductor element 审中-公开
标题翻译：硅碳化硅半导体元件
公开(公告)号：JP2004253427A
公开(公告)日：2004-09-09
申请号：JP2003039317
申请日：2003-02-18
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： TAKAHASHI KUNIMASA , KITAHATA MAKOTO , KUSUMOTO OSAMU , UCHIDA MASAO , YAMASHITA MASAYA
IPC分类号： H01L29/78
摘要： PROBLEM TO BE SOLVED: To provide a silicon carbide semiconductor element which can conduct a drain current of high current density and has high source drain breakdown voltage. SOLUTION: The silicon carbide semiconductor element comprises a base layer 4 adjacent to a drift layer 2, a drain layer 3 on a drift layer 2 cortex, a source layer 5 on a base layer 4 cortex and away from the drift layer 2, a surface conductive layer 6 on the base layer 4 and the drift layer 2, a gate electrode 9 located through a gate insulated film 8 on the base layer 4 sandwiched by the drift layer 2 and the source layer 5, and a drain electrode 11 and a source electrode 10 which are connected with the drain layer 3 and the source layer 5, respectively. The semiconductor element includes a depletion forming layer 7 between the base layer 4 and the drain layer 3. COPYRIGHT: (C)2004,JPO&NCIPI
摘要翻译：要解决的问题：提供可以传导高电流密度的漏电流并具有高源极漏极击穿电压的碳化硅半导体元件。解决方案：碳化硅半导体元件包括与漂移层2相邻的基极层4，漂移层2皮层上的漏极层3，基底层4皮质并远离漂移层2的源极层5 ，基底层4和漂移层2上的表面导电层6，位于由漂移层2和源极层5夹持的基底层4上的栅极绝缘膜8的栅电极9和漏极电极11 以及分别与漏极层3和源极层5连接的源电极10。半导体元件包括在基底层4和漏极层3之间的耗尽形成层7.版权所有：（C）2004，JPO＆NCIPI

7. 发明专利

JP2004214368A Semiconductor device 审中-公开
公开(公告)号：JP2004214368A
公开(公告)日：2004-07-29
申请号：JP2002381248
申请日：2002-12-27
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： UCHIDA MASAO , KITAHATA MAKOTO , MIYANAGA RYOKO , TAKAHASHI KUNIMASA , KUSUMOTO OSAMU , YAMASHITA MASAYA , NOBORI KAZUHIRO
IPC分类号： H01L23/34 , H01L23/48
CPC分类号： H01L24/32 , H01L2224/14 , H01L2224/14181 , H01L2224/16245 , H01L2224/32245 , H01L2224/48247 , H01L2224/48472 , H01L2224/73257 , H01L2224/73265 , H01L2224/81385 , H01L2224/83385 , H01L2924/12032 , H01L2924/1301 , H01L2924/13055 , H01L2924/13091 , H01L2924/181 , H01L2924/00 , H01L2924/00012
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device capable of miniaturizing while securing thermal reliability in the other part of a semiconductor element. SOLUTION: A package 10 (semiconductor device) is provided with the semiconductor element 11 comprising a wide cap semiconductor, a metal ball 12 contacted with the lower surface of the semiconductor element 11, a lead frame 13 electrically connected to the semiconductor element 11 through the metal ball 12 and having a first terminal 15 at one part among end parts, a wire 17 connected to the upper surface of the semiconductor element 11, a second terminal 16 connected to the wire 17, and resin 18 for filling the inside of the package 10. A region wherein the metal ball 12 is not provided between the semiconductor element 11 and the lead frame 13 is a gap 14 having a thermal resistance. Since the gap 14 is provided, heat generated in the semiconductor element 11 is hardly conducted to the lead frame 13. COPYRIGHT: (C)2004,JPO&NCIPI

8. 发明专利

JP2004096061A Semiconductor device and its manufacturing method 有权
公开(公告)号：JP2004096061A
公开(公告)日：2004-03-25
申请号：JP2003021692
申请日：2003-01-30
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： KUSUMOTO OSAMU , KITAHATA MAKOTO , TAKAHASHI KUNIMASA , YAMASHITA MASAYA , MIYANAGA RYOKO , UCHIDA MASAO
IPC分类号： H01L21/28 , H01L21/04 , H01L21/336 , H01L21/338 , H01L21/82 , H01L21/822 , H01L21/8232 , H01L21/8234 , H01L27/04 , H01L27/06 , H01L27/095 , H01L29/12 , H01L29/24 , H01L29/36 , H01L29/45 , H01L29/47 , H01L29/772 , H01L29/78 , H01L29/812 , H01L29/872 , H01L21/06
CPC分类号： H01L29/7813 , H01L21/0485 , H01L21/8213 , H01L27/0605 , H01L27/0629 , H01L29/1029 , H01L29/105 , H01L29/1608 , H01L29/365 , H01L29/41766 , H01L29/66068 , H01L29/7725 , H01L29/7828 , H01L29/7838 , H01L29/812 , H01L29/872 , Y10S438/931
摘要： PROBLEM TO BE SOLVED: To decrease the manufacturing cost of a semiconductor device which uses a compound semiconductor. SOLUTION: A storage MISFET comprises a high resistance SiC layer 102 epitaxially grown on a SiC wafer 101, a P-type well region 103, an n-type storage channel layer 104 having a multiple δ dope layer formed on the surface region of the region 103, a contact region 105, a gate insulation film 108, and a gate electrode 110. The layer 104 has a structure in which an undoped layer 104b and a δ dope layer 104a where the carriers can leach to the layer 104b by the quantum effect are alternately laminated. A source electrode 111 which enter the layer 104 and the region 105 to directly contact the region 105. As any source region formed by ion implantation is not required, the manufacturing cost is decreased. COPYRIGHT: (C)2004,JPO

9. 发明专利

JP2007035736A Semiconductor device and electrical apparatus 审中-公开
标题翻译：半导体器件和电器
公开(公告)号：JP2007035736A
公开(公告)日：2007-02-08
申请号：JP2005213696
申请日：2005-07-25
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： KITAHATA MAKOTO , KUSUMOTO OSAMU , UCHIDA MASAO , YAMASHITA MASAYA , HASHIMOTO SHIN
IPC分类号： H01L27/04 , H01L21/28 , H01L29/12 , H01L29/41 , H01L29/47 , H01L29/78 , H01L29/872
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device and an electrical apparatus for simultaneously realizing high-speed switching operation and reduction in energy loss, and ensuring superior resistance for concentration of current, based on the back electromotive force due to the inductance load of electrical apparatus.
SOLUTION: The semiconductor device 100 comprises a semiconductor layer 3 formed of a first conductivity-type wide-band gap semiconductor, a transistor cell 101T where a vertical field effect transistor 102 is formed for moving charged carrier in the thickness direction of the semiconductor layer 3, and a diode cell 31 is formed where a Schottky diode 103, formed with Schottky junction of a Schottky electrode 9 to the semiconductor layer 3. On the semiconductor layer 3, a plurality of square sub-regions 101 are defined in the plan view, through an arrangement such that sub-regions are allocated in the two directions crossing with each other with virtual boundary lines. Moreover, the transistor cell 101T formed of the remaining portions of the sub-regions 101 and the diode cell 31 formed of the cut-away portions are also defined, in such a manner as to cut away the four corners of sub-regions 101.
COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供一种用于同时实现高速开关操作和降低能量损耗的半导体器件和电气设备，并且基于由于电感的反电动势确保优异的电流集中电阻电器负载。解决方案：半导体器件100包括由第一导电型宽带隙半导体形成的半导体层3，晶体管单元101T，其形成垂直场效应晶体管102，用于沿带电方向的宽度方向移动带电载体半导体层3和二极管单元31形成有肖特基二极管103，肖特基二极管103由肖特基电极9的肖特基结构形成到半导体层3.在半导体层3上，多个正方形的子区域101被限定在平面图，通过这样的布置，使得在具有虚拟边界线的彼此交叉的两个方向上分配子区域。此外，由切除部分形成的子区域101的剩余部分和二极管单元31形成的晶体管单元101T也以切除子区域101的四个角的方式限定。版权所有（C）2007，JPO＆INPIT

10. 发明专利

JP2006210818A Semiconductor element and its manufacturing method 审中-公开
标题翻译：半导体元件及其制造方法
公开(公告)号：JP2006210818A
公开(公告)日：2006-08-10
申请号：JP2005023755
申请日：2005-01-31
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： YAMASHITA MASAYA , KITAHATA MAKOTO , KUSUMOTO OSAMU , TAKAHASHI KUNIMASA , UCHIDA MASAO , MIYANAGA RYOKO , HASHIMOTO KOICHI
IPC分类号： H01L21/318 , H01L21/28 , H01L21/283 , H01L21/336 , H01L21/822 , H01L27/04 , H01L29/12 , H01L29/78
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor element which has high channel mobility and a method in which such a semiconductor element can be manufactured through a practical process with superior mass-productivity.
SOLUTION: The manufacturing method includes a step of forming an oxide layer 11 on a silicon carbide layer 3 (A), and a step of forming a nitride-containing oxide layer 12 by subjecting the oxide layer 11 to nitrogen processing and thus incorporating nitrogen in the oxide layer 11 (B). The nitrogen processing includes a step of exposing the surface of the nitrogen layer 11 to nitrogen-containing gas prepared, by diluting gas containing at least one of nitrogen oxide gas and ammonium gas with inert gas having smaller molecular weight than argon at a temperature of 1,100 to 1,300°C.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供一种具有高通道迁移率的半导体元件以及通过实际工艺制造这种半导体元件的方法，其具有优异的批量生产率。解决方案：制造方法包括在碳化硅层3（A）上形成氧化物层11的步骤，以及通过对氧化物层11进行氮处理形成含氮化物的氧化物层12的步骤在氧化物层11（B）中掺入氮。氮处理包括将氮层11的表面暴露于含氮气体的步骤，通过在1100℃的温度下稀释含有比氩气分子量小的惰性气体的氮氧化物气体和铵气体中的至少一种的气体至1300℃。版权所有（C）2006，JPO＆NCIPI

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