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1. 发明专利

JP2006196494A Electrical equipment 审中-公开
标题翻译：电子设备
公开(公告)号：JP2006196494A
公开(公告)日：2006-07-27
申请号：JP2005003469
申请日：2005-01-11
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： KITAHATA MAKOTO , KUSUMOTO OSAMU , UCHIDA MASAO , TAKAHASHI KUNIMASA , YAMASHITA MASAYA , MIYANAGA RYOKO , HASHIMOTO KOICHI
IPC分类号： H01L23/36
CPC分类号： H01L2224/48137 , H01L2224/73265 , H01L2924/12032 , H01L2924/1301 , H01L2924/13055 , H01L2924/13091 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide electrical equipment where efficiency of heat transfer design using a semiconductor module is made high by installing the semiconductor module using a wide band gap semiconductor to a member heated to a range of 90°C to 400°C. SOLUTION: Electrical equipment 130 is provided with the semiconductor module 110 using the wide band gap semiconductor and a member to be heated 13 used in the temperature range of 90°C to 400°C. The semiconductor module 110 is installed on the member to be heated 13 which is heated to the temperature range. Thus, the semiconductor module 110 is heated. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：为了提供使用半导体模块的传热设计效率高的电气设备，其通过使用宽带隙半导体将半导体模块安装到加热到90℃至400℃的范围的构件 C。解决方案：电气设备130使用宽带隙半导体和在90℃至400℃的温度范围内使用的待加热构件13设置半导体模块110。将半导体模块110安装在被加热到该温度范围的构件13上。因此，半导体模块110被加热。版权所有（C）2006，JPO＆NCIPI

2. 发明专利

JP2006120897A Silicon carbide element and its manufacturing method 审中-公开
标题翻译：硅碳元素及其制造方法
公开(公告)号：JP2006120897A
公开(公告)日：2006-05-11
申请号：JP2004307883
申请日：2004-10-22
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： TAKAHASHI KUNIMASA , KITAHATA MAKOTO , KUSUMOTO OSAMU , UCHIDA MASAO , YAMASHITA MASAYA , MIYANAGA RYOKO , HASHIMOTO KOICHI
IPC分类号： H01L21/336 , H01L21/205 , H01L29/12 , H01L29/78
摘要： PROBLEM TO BE SOLVED: To restrain the deterioration of element characteristics caused due to basal plane dislocation, existing in the semiconductor substrate, in a semiconductor element.
SOLUTION: The semiconductor element comprises the semiconductor substrate 11, a semiconductor layer 20 formed on the surface of the semiconductor substrate 11, a gate insulating film 16 formed on the semiconductor layer 20, and a gate electrode 19 insulated from the semiconductor layer 20 via the gate insulating film 16. Density of the basal plane dislocation is ≥10
4 cm
-2 in the semiconductor substrate 11, and the density of the basal plane dislocation is ≤10
3 cm
-2 at a portion on the surface of the semiconductor layer 20 facing the gate electrode 19.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：为了抑制在半导体元件中存在于半导体衬底中的由于基底位错引起的元件特性的劣化。解决方案：半导体元件包括半导体衬底11，形成在半导体衬底11的表面上的半导体层20，形成在半导体层20上的栅极绝缘膜16和与半导体层绝缘的栅电极19 通过栅极绝缘膜16.半导体衬底11中的基面位错的密度为≥10 4 cm -2 ，并且基面位错的密度为在半导体层20的与栅极电极19相对的表面上的部分，≤10 3 cm -2 。版权所有（C）2006，JPO＆NCIPI

3. 发明专利

JP2006066438A Semiconductor device and its manufacturing method 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2006066438A
公开(公告)日：2006-03-09
申请号：JP2004243852
申请日：2004-08-24
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： YAMASHITA MASAYA , KITAHATA MAKOTO , KUSUMOTO OSAMU , TAKAHASHI KUNIMASA , UCHIDA MASAO , MIYANAGA RYOKO , HASHIMOTO KOICHI
IPC分类号： H01L29/78 , H01L21/336 , H01L29/12
CPC分类号： H01L29/7828 , H01L29/66666
摘要： PROBLEM TO BE SOLVED: To provide a high reliability semiconductor device by improving the insulating breakdown voltage in a gate insulating film. SOLUTION: The semiconductor device is provided with a second semiconductor layer 44 formed on a first semiconductor layer 42, a gate electrode 53 which is electrically insulated from the first semiconductor layer 42, a source electrode 51, a drain electrode 55, a gate insulating film 49, a second conductivity-type source region 47 in which at least a part is formed in a first conductivity-type well region 45 and which is electrically brought into contact with the source electrode 51, and a drift region 43. A prescribed region in the second semiconductor layer 44 is an accumulation channel region, including a second conductive layer. It is formed inside the well region 45 and has an auxiliary source region 48 which is brought into contact with the source region 47; the source region 47 is not overlapped by the gate electrode 53; and a part of the auxiliary source region 48 is overlapped by the gate electrode 53. The total dose amount of the auxiliary source region 48 is smaller than that of the source region 47. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：通过提高栅极绝缘膜中的绝缘击穿电压来提供高可靠性的半导体器件。解决方案：半导体器件设置有形成在第一半导体层42上的第二半导体层44，与第一半导体层42电绝缘的栅电极53，源电极51，漏电极55，栅极绝缘膜49，第二导电型源极区47，其中至少一部分形成在第一导电类型阱区45中，并且与源电极51电接触;以及漂移区43.A 第二半导体层44中的规定区域是包括第二导电层的堆积沟道区域。形成在阱区45的内部，并具有与源极区域47接触的辅助源极区域48; 源极区域47不与栅电极53重叠; 并且辅助源极区域48的一部分与栅电极53重叠。辅助源极区域48的总剂量量小于源极区域47的总剂量。（C）2006，JPO和NCIPI

4. 发明专利

JP2006024880A Semiconductor device and its manufacturing method 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2006024880A
公开(公告)日：2006-01-26
申请号：JP2004377299
申请日：2004-12-27
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： MIYANAGA RYOKO , UCHIDA MASAO , TAKAHASHI KUNIMASA , KITAHATA MAKOTO , KUSUMOTO OSAMU , YAMASHITA MASAYA , HASHIMOTO KOICHI
IPC分类号： H01L21/28 , H01L21/3205 , H01L21/336 , H01L21/338 , H01L23/52 , H01L29/06 , H01L29/12 , H01L29/417 , H01L29/47 , H01L29/78 , H01L29/812 , H01L29/872
CPC分类号： H01L21/049 , H01L21/0485 , H01L24/05 , H01L2224/04042 , H01L2224/48463 , H01L2924/12032 , H01L2924/1306 , H01L2924/13063 , H01L2924/13091 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To suppress the stripping of an electrode connected with a silicon carbide layer, while securing good contact with the silicon carbide layer. SOLUTION: The manufacturing method of a semiconductor device having a silicon carbide layer 11 includes a step of forming a conductive layer 21 on the silicon carbide layer 11 (A); a step of forming an alloy layer comprising a reaction layer 12 making contact with the silicon carbide layer 11 and a silicide layer 23, by causing the conductive layer 21 to react with the silicon carbide layer 11 (B); a step of exposing at least a part of the surface of the reaction layer 12, by removing at least a part of the silicide layer 23 (C); and a step of forming an electrode layer 13 on the surface of the exposed reaction layer 12. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：为了抑制与碳化硅层连接的电极的剥离，同时确保与碳化硅层的良好接触。解决方案：具有碳化硅层11的半导体器件的制造方法包括在碳化硅层11（A）上形成导电层21的步骤。通过使导电层21与碳化硅层11（B）反应，形成包含与碳化硅层11接触的反应层12和硅化物层23的合金层的工序; 通过去除至少一部分硅化物层23（C）来暴露反应层12的至少一部分表面的步骤; 以及在暴露的反应层12的表面上形成电极层13的步骤。版权所有（C）2006，JPO＆NCIPI

5. 发明专利

JP2006019608A Misfet device 审中-公开
标题翻译： MISFET器件
公开(公告)号：JP2006019608A
公开(公告)日：2006-01-19
申请号：JP2004197738
申请日：2004-07-05
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： KUSUMOTO OSAMU , UCHIDA MASAO , KITAHATA MAKOTO , MIYANAGA RYOKO , TAKAHASHI KUNIMASA , YAMASHITA MASAYA , HASHIMOTO KOICHI
IPC分类号： H01L29/78 , H01L21/336 , H01L29/12
摘要： PROBLEM TO BE SOLVED: To restrain the breakdown of a gate insulating film on a space between adjacent well regions without increasing on-resistance and complicating a manufacturing process in a MISFET device.
SOLUTION: The MISFET device has a first conductivity type semiconductor substrate 11, a semiconductor layer 10 provided on the main surface of the semiconductor substrate 11, a gate insulating film 16 and a plurality of source electrodes 19 formed on the semiconductor layer 10, and gate electrode structures 9, 37 provided on the gate insulating film 16. It has a plurality of well regions 13 spaced out in the semiconductor layer 10, a first conductivity type source region 15 which is in electric contact with a corresponding electrode of a plurality of source electrodes 19, and a first conductivity type high resistance region 12 constituted of a part of the semiconductor layer 10 wherein a plurality of the well regions 13 are not formed. The gate electrode structures 9, 37 have openings 8 at the center between adjacent well regions 13.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：为了抑制相邻阱区域之间的栅极绝缘膜的破坏，而不增加导通电阻并使MISFET器件中的制造工艺复杂化。解决方案：MISFET器件具有第一导电类型半导体衬底11，设置在半导体衬底11的主表面上的半导体层10，栅极绝缘膜16和形成在半导体层10上的多个源电极19 以及设置在栅极绝缘膜16上的栅电极结构9,37。它具有在半导体层10中间隔的多个阱区13，与第一导电类型源区15电接触的第一导电类型源区15，多个源电极19以及由未形成多个阱区13的半导体层10的一部分构成的第一导电型高电阻区域12。栅电极结构9,37在相邻的阱区13之间的中心具有开口8.版权所有：（C）2006，JPO＆NCIPI

6. 发明专利

JP2005353771A MANUFACTURING METHOD OF SiC SEMICONDUCTOR DEVICE 有权
标题翻译： SiC半导体器件的制造方法
公开(公告)号：JP2005353771A
公开(公告)日：2005-12-22
申请号：JP2004171808
申请日：2004-06-09
申请人： Kyoto Univ , Matsushita Electric Ind Co Ltd , 国立大学法人京都大学 , 松下電器産業株式会社
发明人： KITAHATA MAKOTO , TAKAHASHI KUNIMASA , MATSUNAMI HIROYUKI , KIMOTO TSUNENOBU
IPC分类号： H01L29/16 , H01L21/265
CPC分类号： H01L21/046
摘要： PROBLEM TO BE SOLVED: To provide the manufacturing method of an SiC semiconductor device realizing a high activating rate while maintaining a smooth surface as it is. SOLUTION: An ion implantation layer 6 is formed by driving aluminum ion 5 into a part of an SiC layer with a smoothed surface or an n-type drift layer 2. A carbon film 7 is formed on the n-type drift layer 2 and the ion implantation layer 6 through spattering method, and then, activating anneal is effected under a condition that the n-type drift layer 2 and the ion implantation layer 6 are covered by the carbon film 7 to change the ion implantation layer 6 into a p-type well region 8. Thereafter, a carbon film 7 is removed whereby the SiC layer can be obtained with the smooth surface substantially not changed from a condition before applying the activating annealing. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供实现高激活率同时保持光滑表面的SiC半导体器件的制造方法。解决方案：通过将铝离子5驱动到具有平滑表面或n型漂移层2的SiC层的一部分中而形成离子注入层6.碳膜7形成在n型漂移层 2和离子注入层6通过溅射方法，然后在n型漂移层2和离子注入层6被碳膜7覆盖以将离子注入层6改变为然后，除去碳膜7，由此可以获得具有平滑表面的SiC层，与施加激活退火之前的条件基本上没有变化。版权所有（C）2006，JPO＆NCIPI

7. 发明专利

JP2005251997A Semiconductor device and its manufacturing method 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2005251997A
公开(公告)日：2005-09-15
申请号：JP2004060617
申请日：2004-03-04
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： NOBORI KAZUHIRO , KITAHATA MAKOTO
IPC分类号： H01L23/29 , H01L23/31 , H05K3/32
CPC分类号： H01L2224/45124 , H01L2224/45144 , H01L2224/48091 , H01L2224/48472 , H01L2224/73265 , H01L2924/13055 , H01L2924/13091 , H01L2924/30107 , H01L2924/00014 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device with enhanced heat resistance, and to provide its manufacturing method. SOLUTION: An assembly 5 is so constituted that the semiconductor device joins a thermal diffusion board 3 and a projection electrode 2 to electrodes 1a and 1b, on the both top and rear surface sides of the semiconductor device 1 and encloses them with a piece of glass 4. An assembly 10 is constituted of the thermal diffusion board 3 and the projection electrode 2 of the semiconductor assembly 5 which are mounted in a circuit board 6. By constituting semiconductor the device 10 only from an inorganic material, the heat resistance inside the semiconductor device 10 is enhanced, and the reliability of the semiconductor device for switching in a power circuit and the like is improved. COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：提供具有增强的耐热性的半导体器件，并提供其制造方法。解决方案：组件5被构造成使得半导体器件将半导体器件1的顶表面侧和后表面侧的热扩散板3和突起电极2连接到电极1a和1b，并且将其包围组件10由安装在电路板6中的半导体组件5的热扩散板3和突起电极2构成。通过仅由无机材料构成半导体器件10，耐热性增强了半导体器件10的内部，提高了用于切换电源电路等的半导体器件的可靠性。版权所有（C）2005，JPO＆NCIPI

8. 发明专利

JP2005136386A Silicon carbide-oxide laminate, manufacturing method therefor, and semiconductor device 审中-公开
标题翻译：碳化硅氧化物层压板，其制造方法和半导体器件
公开(公告)号：JP2005136386A
公开(公告)日：2005-05-26
申请号：JP2004271321
申请日：2004-09-17
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： YAMASHITA MASAYA , KITAHATA MAKOTO , KUSUMOTO OSAMU , TAKAHASHI KUNIMASA , UCHIDA MASAO , MIYANAGA RYOKO
IPC分类号： H01L21/318 , H01L21/336 , H01L29/12 , H01L29/78
CPC分类号： H01L29/7828
摘要： PROBLEM TO BE SOLVED: To provide a silicon carbide-oxide laminate for producing a low-loss high-reliability MISFET or the like, a manufacturing method therefor, and a semiconductor device.
SOLUTION: A gate insulating film 7' which is an oxide layer mainly made of SiO
2 is formed on a SiC substrate 10 through thermal oxidation, and then a resultant structure is annealed in an inert gas atmosphere in a chamber 20. Thereafter, the SiC substrate 10 is placed in a chamber 30 which has a vacuum pump 31, and the silicon carbide-oxide layered structure A is exposed to an NO gas atmosphere, of reduced pressure at a high temperature which is higher than 1,100°C but lower than 1,250°C, whereby nitrogen diffuses to the gate insulating film 7'. As a result, a gate insulating film 7 which is a group V element, containing oxide layer, the lower part of which includes a region with high nitrogen concentration, and the relative dielectric constant of which is 3.0 or higher, is obtained. The interface state density of an interface region between the V-group element containing oxide layer and the silicon carbide layer decreases.
COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：提供用于制造低损耗高可靠性MISFET等的碳化硅 - 氧化物层压体，其制造方法和半导体器件。解决方案：通过热氧化在SiC衬底10上形成作为主要由SiO 2 制成的氧化物层的栅极绝缘膜7'，然后将所得结构在惰性气体之后，将SiC基板10放置在具有真空泵31的室30中，并且将碳化硅 - 氧化物层状结构A暴露于NO气体气氛中，在高温下进行减压高于1100℃但低于1250℃，由此氮扩散到栅绝缘膜7'。结果，获得了包含氧化物层的V族元素的栅极绝缘膜7，其下部包括具有高氮浓度的区域，并且其相对介电常数为3.0或更高。含V族元素的氧化物层和碳化硅层之间的界面区域的界面态密度降低。版权所有（C）2005，JPO＆NCIPI

9. 发明专利

JP2005056868A Method of manufacturing silicon carbide semiconductor device 审中-公开
标题翻译：制造碳化硅半导体器件的方法
公开(公告)号：JP2005056868A
公开(公告)日：2005-03-03
申请号：JP2001167974
申请日：2001-06-04
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： KUSUMOTO OSAMU , YOKOGAWA TOSHIYA , UCHIDA MASAO , YAMASHITA MASAYA , MIYANAGA RYOKO , KITAHATA MAKOTO , TAKAHASHI KUNIMASA
IPC分类号： H01L21/302 , H01L21/04 , H01L21/3065 , H01L21/336 , H01L29/12 , H01L29/24 , H01L29/423 , H01L29/78
CPC分类号： H01L29/7813 , H01L29/1608 , H01L29/42368 , H01L29/66068
摘要： PROBLEM TO BE SOLVED: To solve the problem that, when trench etching is performed on the surface of a silicon carbide semiconductor substrate while a high etching rate is maintained at the time of forming a gate oxide film on the surface of a trench in a trench MOS, a micro-trench is produced in the bottom section of the end section of the trench and electric field concentration occurs in the micro-trench due to the small radius of curvature of the micro-trench and lowers the withstand voltage of the gate oxide film.
SOLUTION: After a first etching step is performed by using a usual Al mask, a second etching step is performed for etching the whole surface of the silicon carbide semiconductor substrate after removing the Al mask.
COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：解决的问题为了解决在对碳化硅半导体基板的表面进行沟槽蚀刻的同时在沟槽表面形成栅极氧化膜时保持高的蚀刻速度的问题在沟槽MOS中，在沟槽的端部的底部产生微沟槽，由于微沟槽的小曲率半径而在微沟槽中发生电场集中，并且降低了栅氧化膜。解决方案：在通过使用通常的Al掩模进行第一蚀刻步骤之后，执行第二蚀刻步骤，以在去除Al掩模之后蚀刻碳化硅半导体衬底的整个表面。版权所有（C）2005，JPO＆NCIPI

10. 发明专利

JP2005026408A Semiconductor element and its fabricating process 审中-公开
标题翻译：半导体元件及其制造工艺
公开(公告)号：JP2005026408A
公开(公告)日：2005-01-27
申请号：JP2003189468
申请日：2003-07-01
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： UCHIDA MASAO , KITAHATA MAKOTO , TAKAHASHI KUNIMASA , KUSUMOTO OSAMU , YAMASHITA MASAYA , MIYANAGA RYOKO
IPC分类号： H01L29/872 , H01L29/47 , H01L29/861
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor element having a high breakdown voltage, and to provide its fabricating process.
SOLUTION: A Shottky diode 10 comprises a semiconductor substrate 11 of n-type 4H-SiC, a first SiC layer 12 of 4H-SiC provided on the semiconductor substrate 11, a Schottky electrode 14 of nickel provided on the first SiC layer 12, and an ohmic electrode 15 of nickel provided on the lower surface of the semiconductor substrate 11. A high concentration layer 12b having n-type impurities at a concentration higher than that in other regions is provided at a part of the first SiC layer 12. Since an electric field concentrating in a region where the lower end part of the Schottky electrode 14 touches the first SiC layer 12 can be relaxed, breakdown voltage can be enhanced.
COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：提供具有高击穿电压的半导体元件，并提供其制造工艺。解决方案：肖特基二极管10包括n型4H-SiC的半导体衬底11，设置在半导体衬底11上的4H-SiC的第一SiC层12，设置在第一SiC层上的镍肖特基电极14 设置在半导体基板11的下表面上的镍的欧姆电极15.在第一SiC层12的一部分设置有浓度高于其它区域的n型杂质的高浓度层12b 由于可以放松集中在肖特基电极14的下端部与第一SiC层12接触的区域的电场，能够提高击穿电压。版权所有（C）2005，JPO＆NCIPI

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