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1. 发明专利

JP2006196807A Vacuum deposition apparatus and thin-film formation method 审中-公开
标题翻译：真空沉积装置和薄膜形成方法
公开(公告)号：JP2006196807A
公开(公告)日：2006-07-27
申请号：JP2005008665
申请日：2005-01-17
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： TAKAHASHI KUNIMASA , KITAHATA MAKOTO , KUSUMOTO OSAMU , UCHIDA MASAO , YAMASHITA MASAYA , MIYANAGA RYOKO , HASHIMOTO KOICHI , OSADA KAORU
IPC分类号： H01L21/205 , C23C16/42 , C23C16/44 , C23C16/46
摘要： PROBLEM TO BE SOLVED: To provide a vacuum deposition apparatus and a thin-film formation method capable of stably forming a thin film without any defects and dislocation on a substrate.
SOLUTION: The vacuum deposition apparatus 110 comprises a vacuum chamber 4, where internal pressure has been reduced; a susceptor 1 that is arranged inside the vacuum chamber 4 and retains the substrate; opposing members 2 that sandwich the substrate, oppose the susceptor 1 with a prescribed gap P, and are arranged inside the vacuum chamber 4; a heating means 3 for performing the induction heating of the susceptor 1; a gas supply port 4c for supplying raw material gas to the inside of the vacuum chamber; and a gas discharge port for discharging gas inside the vacuum chamber. In this case, a surface for retaining the substrate of the susceptor 1 faces downward, and the opposing members 2 are arranged with the prescribed gap P at the lower portion of the susceptor 1.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供一种能够在基板上没有任何缺陷和位错地稳定地形成薄膜的真空沉积设备和薄膜形成方法。解决方案：真空沉积设备110包括真空室4，其中内部压力已经降低; 设置在真空室4内并保持基板的感受体1; 夹着基板的相对构件2以规定的间隙P与基座1相对配置在真空室4的内部。用于进行基座1的感应加热的加热装置3; 用于将原料气体供给到真空室的内部的气体供给口4c; 以及用于在真空室内排出气体的气体排出口。在这种情况下，用于保持基座1的基板的表面朝下，相对的构件2在基座1的下部以规定的间隙P布置。（C）2006，JPO＆NCIPI

2. 发明专利

JP2006196806A Vacuum deposition apparatus and thin-film formation method 审中-公开
标题翻译：真空沉积装置和薄膜形成方法
公开(公告)号：JP2006196806A
公开(公告)日：2006-07-27
申请号：JP2005008664
申请日：2005-01-17
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： TAKAHASHI KUNIMASA , KITAHATA MAKOTO , KUSUMOTO OSAMU , UCHIDA MASAO , YAMASHITA MASAYA , MIYANAGA RYOKO , HASHIMOTO KOICHI , OSADA KAORU
IPC分类号： H01L21/205 , C23C16/42 , C23C16/44 , C23C16/46
摘要： PROBLEM TO BE SOLVED: To provide a vacuum deposition apparatus that is superior in the reproducibility of film thickness, or the like, and can form a thin film without any defects and transposition on a substrate while securing a high deposition speed, and to provide a method for forming the thin film. SOLUTION: The vacuum deposition apparatus 110 comprises a vacuum chamber 4 capable of reducing internal pressure; a susceptor 1 that is arranged inside the vacuum chamber 4 and retains the substrate 6a; opposing members 2 that oppose a surface for retaining the substrate 6a of the susceptor 1 with a prescribed gap 9, and are arranged inside the vacuum chamber 4; a heating means 3 for performing the induction heating of the susceptor 1; a gas supply port 7 for supplying feed gas to the inside of the vacuum chamber 4; and a gas discharge port 4c for discharging gas inside the vacuum chamber 4. In this case, heat based on heat conduction is transferred from the susceptor 1 to the substrate 6a, and the raw material gas passing through the gas supply port 7 flows in the gap 9 from the periphery of the susceptor 1 to the center section. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供一种真空沉积设备，其膜厚等的再现性优异，并且可以在确保高沉积速度的同时在基板上形成没有任何缺陷和转置的薄膜，以及以提供形成薄膜的方法。解决方案：真空沉积设备110包括能够降低内部压力的真空室4; 设置在真空室4内并保持基板6a的基座1; 相对的构件2，其相对于用于保持基座1的基板6a的表面具有规定的间隙9，并且布置在真空室4的内部; 用于进行基座1的感应加热的加热装置3; 用于向真空室4的内部供给进料气体的气体供给口7; 以及用于在真空室4内排出气体的气体排出口4c。在这种情况下，基于热传导的热量从基座1传递到基板6a，并且通过气体供给口7的原料气体流入间隙9从基座1的周边到中心部分。版权所有（C）2006，JPO＆NCIPI

3. 发明专利

JP2006066439A Semiconductor device and its manufacturing method 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2006066439A
公开(公告)日：2006-03-09
申请号：JP2004243853
申请日：2004-08-24
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： YAMASHITA MASAYA , KITAHATA MAKOTO , KUSUMOTO OSAMU , TAKAHASHI KUNIMASA , UCHIDA MASAO , MIYANAGA RYOKO , HASHIMOTO KOICHI
IPC分类号： H01L29/78 , H01L21/265 , H01L21/266 , H01L21/336 , H01L29/12
摘要： PROBLEM TO BE SOLVED: To provide a high reliability semiconductor device by improving the insulating breakdown voltage in a gate insulating film.
SOLUTION: The device is provided with a gate electrode 53 forming a conductive channel in a semiconductor layer 42, a source electrode 51 and a drain electrode 55 which are electrically connected via the conductive channel, a gate insulating film 49 installed in between the semiconductor layer 42 and the gate electrode 53, a second conductive source region 47, which is formed inside a first conductive well region 45 and is electrically brought into contact with the source electrode 51, and a second conductive drift region 43. The semiconductor layer 42 has a second conductivity-type auxiliary source region 48 which is brought into contact with the source region 47; the source region 47 is not overlapped with the gate electrode 53, and a part of the auxiliary source region 48 is overlapped with the gate electrode 53; and the total dose of the auxiliary source region 48 is smaller than that of the source region 47.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：通过提高栅极绝缘膜中的绝缘击穿电压来提供高可靠性的半导体器件。解决方案：该器件设置有在通过导电通道电连接的半导体层42，源电极51和漏电极55中形成导电通道的栅电极53，安装在其间的栅极绝缘膜49 半导体层42和栅电极53，形成在第一导电阱区45内部并与源电极51电接触的第二导电源区47和第二导电漂移区43.半导体层 42具有与源极区域47接触的第二导电型辅助源极区域48; 源极区域47不与栅电极53重叠，并且辅助源极区域48的一部分与栅电极53重叠; 并且辅助源区48的总剂量小于源区47的总剂量。版权所有：（C）2006，JPO和NCIPI

4. 发明专利

JP2006049668A Semiconductor device and manufacturing method therefor 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2006049668A
公开(公告)日：2006-02-16
申请号：JP2004230267
申请日：2004-08-06
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： TAKAHASHI KUNIMASA , KITAHATA MAKOTO , KUSUMOTO OSAMU , UCHIDA MASAO , YAMASHITA MASAYA , MIYANAGA RYOKO , HASHIMOTO KOICHI
IPC分类号： H01L21/76 , H01L21/336 , H01L21/761 , H01L21/762 , H01L21/8234 , H01L27/08 , H01L27/088 , H01L29/12 , H01L29/78 , H01L29/786
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device comprising a power transistor and a control semiconductor element formed on a common substrate in which power loss of the power transistor is reduced sharply as compared with prior art.
SOLUTION: The semiconductor device 200 comprises a transistor 2, and semiconductor elements 10 and 11 for controlling the gate potential of the transistor 2. The transistor 2 and the semiconductor elements 10 and 11 are formed on a common silicon carbide substrate 1, and the semiconductor device 200 further comprises an element isolation region 12 for isolating the transistor 2 and the semiconductor elements 10 and 11 electrically.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供一种半导体器件，其包括形成在公共衬底上的功率晶体管和控制半导体元件，其中功率晶体管的功率损耗与现有技术相比急剧减小。解决方案：半导体器件200包括晶体管2和用于控制晶体管2的栅极电位的半导体元件10和11.晶体管2和半导体元件10和11形成在公共的碳化硅衬底1上，并且半导体器件200还包括用于电隔离晶体管2和半导体元件10和11的元件隔离区域12。版权所有（C）2006，JPO＆NCIPI

5. 发明专利

JP2006041166A Method for forming ion injection mask and silicon carbide device 审中-公开
标题翻译：用于形成离子注入掩模和碳化硅器件的方法
公开(公告)号：JP2006041166A
公开(公告)日：2006-02-09
申请号：JP2004218640
申请日：2004-07-27
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： YAMASHITA MASAYA , KITAHATA MAKOTO , KUSUMOTO OSAMU , TAKAHASHI KUNIMASA , UCHIDA MASAO
IPC分类号： H01L21/266 , H01L21/336 , H01L29/12 , H01L29/78
摘要： PROBLEM TO BE SOLVED: To provide a method for forming an ion implantation mask, having steep side faces whose patterns, are less likely to be tapered.
SOLUTION: A silicon dioxide film 21x as a first film and an Al film 22x as a second film are successively deposited on a substrate, and a resist mask Re1 is formed on the Al film 22x. The resist mask Re1 is used as an etching mask, the Al film 22x is patterned, an Al mask 22 as an intermediate mask is formed, the resist mask Re1 and the Al mask 22 are used as an etching mask; and the silicon dioxide film 21x is patterned so that a silicon dioxide mask 21 can be formed as an ion implantation mask. Afterwards, the resist mask Re1 and the Al mask 22 are removed, and ion is injected into a high resistance SiC layer 2 at a high temperature of 150°C or higher, by using the silicon dioxide mask 21, so that a p-well region 3 being an impurity diffused layer can be formed.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供一种形成离子注入掩模的方法，其具有陡峭的侧面，其图案不太可能是锥形的。解决方案：作为第一膜的二氧化硅膜21x和作为第二膜的Al膜22x依次沉积在基板上，并且在Al膜22x上形成抗蚀剂掩模Re1。使用抗蚀剂掩模Re1作为蚀刻掩模，对Al膜22x进行构图，形成作为中间掩模的Al掩模22，使用抗蚀剂掩模Re1和Al掩模22作为蚀刻掩模; 并且二氧化硅膜21x被图案化，使得可以形成二氧化硅掩模21作为离子注入掩模。然后，除去抗蚀剂掩模Re1和Al掩模22，并通过使用二氧化硅掩模21将离子注入到高电阻SiC层2中，在150℃或更高的高温下，使p阱可以形成作为杂质扩散层的区域3。版权所有（C）2006，JPO＆NCIPI

6. 发明专利

JP2005303010A Silicon carbide element and its manufacturing method 审中-公开
标题翻译：硅碳元素及其制造方法
公开(公告)号：JP2005303010A
公开(公告)日：2005-10-27
申请号：JP2004117111
申请日：2004-04-12
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： TAKAHASHI KUNIMASA , KITAHATA MAKOTO , KUSUMOTO OSAMU , UCHIDA MASAO , YAMASHITA MASAYA , MIYANAGA RYOKO , HASHIMOTO KOICHI
IPC分类号： H01L21/265 , H01L21/336 , H01L29/12 , H01L29/78
CPC分类号： H01L29/1608 , H01L21/046
摘要： PROBLEM TO BE SOLVED: To reduce surface irregularities of a silicon carbide layer generated by activated anneal and to raise dopant concentration in a surface region of the silicon carbide layer without complicating a manufacturing process in the manufacturing method of the silicon carbide element.
SOLUTION: The manufacturing method of the silicon carbide element has (A) a process for preparing a substrate 1 with the silicon carbide layer 2 whose surface is covered with a cap layer 5, (B) a process for forming an impurity dope layer 6 by implanting impurity ion 3 to at least a part of the silicon carbide layer 2 via the cap layer 5, (C) a process for executing activated anneal to the silicon carbide layer 5 covered with the cap layer 5 and (D) a process for removing the cap layer 5 from the substrate 1. In the process (B), the impurity ion 3 is implanted so that the concentration of impurities in a surface region of the silicon carbide layer 2 is at least 80% of a maximum concentration of impurities in the inside of the silicon carbide layer 2.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：为了减少通过活性退火产生的碳化硅层的表面不规则性，并且在碳化硅层的表面区域中提高掺杂剂浓度，而不会使碳化硅元件的制造方法中的制造工艺复杂化。解决方案：碳化硅元件的制造方法具有（A）具有表面被覆盖层5覆盖的碳化硅层2的基板1的制造方法，（B）形成杂质涂料的工序通过经由盖层5将杂质离子3注入到碳化硅层2的至少一部分，（C）对覆盖有盖层5的碳化硅层5进行激活退火的工序，（D）在工序（B）中，注入杂质离子3，使得碳化硅层2的表面区域中的杂质浓度为最大浓度的80％以上的碳化硅层2内的杂质。（C）2006，JPO＆NCIPI

7. 发明专利

JP2005033030A Semiconductor device and manufacturing method thereof 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2005033030A
公开(公告)日：2005-02-03
申请号：JP2003271353
申请日：2003-07-07
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： KUSUMOTO OSAMU , KITAHATA MAKOTO , UCHIDA MASAO , TAKAHASHI KUNIMASA , YAMASHITA MASAYA , MIYANAGA RYOKO
IPC分类号： H01L21/28 , H01L29/12 , H01L29/417 , H01L29/78
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device for preventing the occurrence of a broken electrode, local increase in the electric resistance, and electromigration or the like, and to provide a manufacturing method thereof. SOLUTION: The manufacturing method sequentially forms a high resistance SiC layer 2 and a p-well region 3, carries out epitaxial growing of a channel layer 5 and thereafter, forms a p+ contact region 4 to part of the channel layer 5 and the p-well region 3, forms a source region 6 surrounding sides of the p+ contact region 4 by using an implantation mask open to the upper part of the p+ contact region 4, and thereafter forms a source electrode 8 bridged over the source region 6 and the p+ contact region 4. Since there exists almost no step difference at the base of the source electrode 8, the occurrence of the electromigration of, the break in and the local increase in the electric resistance of the source electrode 8 is suppressed. COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：提供一种用于防止电极断裂发生的半导体器件，电阻的局部增加和电迁移等，并提供其制造方法。解决方案：制造方法依次形成高电阻SiC层2和p阱区域3，进行沟道层5的外延生长，此后，形成沟道层5的一部分的p +接触区域4，以及 p阱区域3通过使用向p +接触区域4的上部开放的注入掩模形成围绕p +接触区域4的侧面的源极区域6，然后形成桥接在源极区域6上的源极电极8 和p +接触区域4.由于在源电极8的基部几乎没有阶梯差，所以抑制了电极的电迁移，电源电极8的电阻的局部增加的发生。版权所有（C）2005，JPO＆NCIPI

8. 发明专利

JP2004014709A Method for manufacturing semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：JP2004014709A
公开(公告)日：2004-01-15
申请号：JP2002164631
申请日：2002-06-05
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： UCHIDA MASAO , KITAHATA MAKOTO , MIYANAGA RYOKO , TAKAHASHI KUNIMASA , KUSUMOTO OSAMU , YAMASHITA MASAYA
IPC分类号： H01L21/28 , H01L21/301 , H01L21/336 , H01L29/12 , H01L29/41 , H01L29/78
摘要： PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor device capable of reducing the occurrence of a defective element due to the breakage or chipping off of a crystal in chip separation. SOLUTION: On a wafer 11 comprising a silicon carbide substrate and a silicon carbide layer, an upper electrode 6 is arranged side by side nearly along a direction Y which is one of cleavage directions and a direction X which is tilted from the cleavage direction by at least 5°. Then, when separating an element formed on the wafer 11 into a plurality of chips 10, the chip is cut off along a separation line 14a which is nearly parallel to the cleavage direction Y and a separation line 14b which is nearly parallel to the direction X. In this case, arranging of the electrode 6 side by side and chip separation are performed with a step formed on the silicon carbide as reference, thereby the cleavage direction is known precisely to reduce occurrence of the breakage or chipping off in the semiconductor chip in chip separation. COPYRIGHT: (C)2004,JPO
摘要翻译：解决问题的方案：提供一种半导体器件的制造方法，该半导体器件能够减少由于芯片分离中的晶体的断裂或破裂而导致的缺陷元件的发生。解决方案：在包括碳化硅衬底和碳化硅层的晶片11上，上电极6大致沿着作为解理方向之一的方向Y和从切割方向倾斜的方向X并排布置方向至少5°。然后，当将形成在晶片11上的元件分成多个芯片10时，沿着与解理方向Y几乎平行的分离线14a切割芯片，并且分离线14b几乎平行于X方向在这种情况下，以碳化硅为基准的台阶形成并列排列电极6和芯片分离，精确地知道切割方向，以减少半导体芯片中的断裂或破裂的发生芯片分离。版权所有（C）2004，JPO

9. 发明专利

JP2003347235A Method of manufacturing semiconductor device 审中-公开
标题翻译：制造半导体器件的方法
公开(公告)号：JP2003347235A
公开(公告)日：2003-12-05
申请号：JP2002153410
申请日：2002-05-28
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： TAKAHASHI KUNIMASA , UCHIDA MASAO , KUSUMOTO OSAMU , YAMASHITA MASAYA , KITAHATA MAKOTO
IPC分类号： H01L29/872 , H01L21/265 , H01L21/338 , H01L29/16 , H01L29/47 , H01L29/812 , H01L29/861
摘要： PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor device having favorable electrical characteristics. SOLUTION: An ion-implanted layer 12 having an impurity ion peak is formed in an SiC substrate 11 by implanting an impurity ion into the substrate 11. Then the substrate 11 is stuck to another SiC substrate 13 and the stuck substrates 11 and 13 are disposed in an annealing furnace and heated in an argon atmosphere. Consequently, the semiconductor device having superior electrical characteristics can be manufactured by using the SiC substrate 11, because a largely damaged upper ion-implanted layer 12b containing the impurity ion at a low concentration of the ion-implanted layer 12 can be removed simultaneously when the annealing is performed. COPYRIGHT: (C)2004,JPO
摘要翻译：要解决的问题：提供一种制造具有良好电气特性的半导体器件的方法。解决方案：通过将杂质离子注入到基板11中，在SiC基板11中形成具有杂质离子峰的离子注入层12.然后将基板11粘贴到另一个SiC基板13上，并将卡住的基板11和 13设置在退火炉中并在氩气气氛中加热。因此，可以通过使用SiC衬底11来制造具有优异的电特性的半导体器件，因为当离子注入层12的低浓度下含有杂质离子的上部离子注入层12b被大量损坏时，进行退火。版权所有（C）2004，JPO

10. 发明专利

JP2008108824A Silicon-carbide semiconductor element and its manufacturing method 审中-公开
标题翻译：硅碳化硅半导体元件及其制造方法
公开(公告)号：JP2008108824A
公开(公告)日：2008-05-08
申请号：JP2006288703
申请日：2006-10-24
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： TAKAHASHI KUNIMASA , KUSUMOTO OSAMU
IPC分类号： H01L29/12 , H01L21/205 , H01L21/336 , H01L29/78
摘要： PROBLEM TO BE SOLVED: To form a facet face consisting of a single crystal face to the face of a silicon carbide layer, and to improve the element characteristics of a silicon-carbide semiconductor element. SOLUTION: The silicon-carbide semiconductor element has a silicon-carbide substrate 1 having an off angle and a silicon carbide layer 10 formed on the silicon-carbide substrate 1. The face of the silicon carbide layer 10 has the facet faces 9 composed of the monocrystal face, and the facet faces 9 are inclined to an envelope on the face of the silicon-carbide substrate 1. The silicon carbide layer 10 contains a first region 10a forming the facet faces 9 and a second region 10b adjacent to lowest sections 9 L on the facet faces 9. Highest sections 9 H in the first region 10a are higher than the face of the second region 10b, and a stepped section with a bottom section more recessed than the lowest sections 9 L in the facet faces 9 is not formed along at least parts of the end sections of the facet faces 9 on the face of the silicon carbide layer 10. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：为了形成由碳化硅层的单面构成的面面，并且提高碳化硅半导体元件的元件特性。解决方案：碳化硅半导体元件具有偏离角的碳化硅衬底1和形成在碳化硅衬底1上的碳化硅层10.碳化硅层10的表面具有面面9 由单晶面组成，小面9与碳化硅衬底1的表面上的外壳倾斜。碳化硅层10包含形成小面9的第一区域10a和邻近最低层的第二区域10b 第一区域10a中的最高部分9 H 高于第二区域10b的表面，并且具有底部的台阶部分在小面9上的最小部分9 L 凹陷的部分不沿着碳化硅层10的表面上的小面9的端部的至少一部分形成。版权所有（C）2008，JPO＆INPIT

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